Serial Data Transfer with Embedded Word Clock to Eliminate Skew
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Solution Overview
Problem
Conventional multi-bit digital data transmission methods require multiple transmission lines, leading to issues like skew and harmonic lock, and often necessitate complex auxiliary means or interrupting data transmission to obtain timing, which complicates the process and increases the risk of errors.
Innovation Solution
A data transfer system that converts multiple bits of parallel data into serial data and combines it with a word clock to create a multi-level logic signal, allowing for reliable transmission over a single transmission line without skew, using a data transmitter with parallel-to-serial conversion, frequency multiplication, and multi-level logic signal generation, and a receiver with comparator and frequency multiplication circuits to extract and synchronize the data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple transmission lines are used to transmit data and clock separately, then data transmission reliability is improved, but device complexity and mounting area increase
Solution Approach 1:
The patent merges the data signal and clock signal into a single transmission line by encoding the clock information within the data stream itself. Specifically, the system transmits multi-bit parallel data as serial data where transitions in the serial data stream encode both data bits and clock timing information, eliminating the need for separate clock transmission lines and reducing overall system complexity while maintaining transmission reliability
Solution Approach 2:
The transmission line is designed to serve multiple functions simultaneously: it transmits both data information and clock synchronization signals through a single channel. The serial data stream is structured so that transitions serve dual purposes of representing data bits and providing clock timing references for serial-to-parallel conversion at the receiver
2Measurement precision
If multiple transmission lines are used for data and clock, then timing accuracy is improved, but skew between lines causes timing errors
Solution Approach 1:
By combining data and clock into a single transmission line, the patent eliminates the skew problem that arises from separate lines. The clock timing is derived directly from transitions in the same signal that carries the data, ensuring that data and clock are inherently synchronized without being subject to differential timing errors between separate transmission paths
3Measurement precision
If special signals are transmitted to obtain timing, then timing information is obtained, but free data transmission is interrupted
Solution Approach 1:
The patent enables continuous data transmission without interruption by embedding clock timing information within the ongoing data stream itself. Rather than pausing data transmission to send separate timing signals or synchronization markers, the system continuously encodes both data and timing information in the same serial signal flow, maintaining uninterrupted productive transmission
4Device complexity
If clock and data are combined in one signal, then transmission lines are reduced, but frequency misidentification and harmonic lock occur
Solution Approach 1:
The system employs feedback mechanisms at the receiver to detect and correct frequency misidentification and prevent harmonic lock. The receiver monitors the incoming serial data stream for transition patterns that encode clock timing, using feedback control to lock onto the correct frequency and phase, thereby ensuring accurate frequency identification even when data and clock are combined in a single signal
Data Source
AI summary
The present invention provides a data transfer system including a data transmitter and a data receiver. The data transmitter converts a plurality of bits of transmission parallel data into serial data and generates a multi-level logic signal representing a plurality of bits of information in one symbol, the information being obtained by combining the serial data with a word clock as one-bit information. The word clock indicates a word delimiter in the serial data. The data receiver receives the transmitted multi-level logic signal, extracts the serial data and the word clock from the signal, and reproduces the parallel data based on the extracted word clock. In the data transfer system, a multi-bit digital signal can be transmitted as one signal including a word clock. Thus, components and mounting space to be allocated to transfer can be reduced.