Encoded Serial Data Bit Error Detector Waveform Capture
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Solution Overview
Problem
Current bit error rate testing for data receivers is unreliable due to clock synchronization issues between test equipment and receivers, leading to false bit error recordings, and lacks the ability to capture waveforms at the time of errors, making it difficult to validate the cause of bit errors.
Innovation Solution
A system that uses a programmable signal source to generate a test encoded serial data stream with known amplitude and jitter characteristics, split to both the device under test and an analyzer, which captures and displays the incident and re-transmitted data streams when a bit error is detected, allowing for validation of bit errors by displaying the associated waveform.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a BERT is used to test the receiver, then bit error rate measurement is enabled, but clock synchronization issues cause false bit errors to be recorded
Solution Approach 1:
A timing recovery mechanism acts as an intermediary between the BERT clock and the receiver clock. This mechanism extracts timing information from the actual received data stream and uses it to retimed-loopback data, thereby mediating the clock synchronization issue and preventing false bit errors caused by clock drift
Solution Approach 2:
The system implements feedback by monitoring the received data stream for timing information and using this information to adjust the retimed-loopback operations. The timing recovery continuously adapts to clock variations by feeding back timing corrections to the loopback mechanism, ensuring synchronization without requiring expensive compensated BERT equipment
2Ease of operation
If the receiver is placed in loopback mode for testing, then receiver functionality can be tested, but clock desynchronization causes erroneous bit error recordings
Solution Approach 1:
The timing recovery mechanism performs preliminary action by pre-synchronizing the loopback operations with the received data stream before bit error detection occurs. By extracting timing information in advance and using it to retimed-loopback data, the system prepares the loopback path to remain synchronized throughout the testing process
Solution Approach 2:
The timing recovery acts as an intermediary layer between the received data and the loopback path, mediating the clock synchronization issue by retimed-loopback data based on extracted timing information, thereby enabling reliable receiver testing without false errors
3Productivity
If standard BERT equipment is used, then bit error counting is possible, but the ability to capture and analyze actual error waveforms is lost
Solution Approach 1:
The system merges the BERT's bit error counting functionality with an oscilloscope's waveform capture capability. By combining these two measurement functions into a unified testing system, the invention enables both efficient error counting and simultaneous capture of the actual analog waveforms at the moment of bit errors, preserving waveform information that would otherwise be lost
4Stability of the object's composition
If re-timed loopback with inserted data strings is used, then clock synchronization is maintained, but the BERT records erroneous bit errors due to the inserted strings
Solution Approach 1:
The invention extracts only the essential timing information from the received data stream and uses it to retimed-loopback data, while taking out (excluding) the problematic practice of inserting special data strings. By removing the data string insertions that cause false errors while retaining the beneficial timing synchronization, the system maintains clock stability without corrupting the bit error measurements
Data Source
AI summary
An encoded serial data bit error analyzer captures the actual waveform of an encoded serial data stream associated with a bit error so that a user may readily validate the cause of the bit error. An encoded serial data stream decoder in the analyzer is modified to provide a signal for a trigger system when a characteristic of a bit error failure is detected. A power splitter produces a pair of incident encoded serial data streams from a programmable test signal, one of which is input to a device under test and the other is input to the analyzer. A re-transmitted encoded serial data stream from the device under test is input to another channel of the analyzer. The encoded serial data stream decoder provides an “error detected” output when a condition occurs in the re-transmitted encoded serial data stream indicative of a bit error. The “error detected” output is used as a trigger signal to capture the incident and re-transmitted encoded serial data waveforms surrounding the detected bit error.