Low-Latency Serial Data Reception Without Clock Domain Crossing
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Solution Overview
Problem
Current network devices experience latency issues due to clock domain crossings when processing serial data, which can introduce delays of at least one or two clock cycles, hindering low-latency operations in latency-sensitive applications.
Innovation Solution
A low-latency network device is designed with a device-wide clock that drives all components, including the receiving physical medium attachment (PMA), symbol timing synchronization module, and physical convergence sublayer (PCS), eliminating the need for clock domain crossings by oversampling serial data asynchronously and synchronizing bit values using a digital phase lock loop, thereby maintaining synchronization with the device-wide clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock domain crossings are used to process serial data from different sources, then data synchronization between different clock domains is achieved, but latency increases by at least one or two clock cycles
Solution Approach 1:
The patent merges multiple clock domains into a single device-wide clock that drives all components including receiving PMA, symbol timing synchronization module, and PCS. This eliminates the need for clock domain crossings between different clock sources, thereby removing the associated latency penalties while maintaining data synchronization through the unified clock domain.
Solution Approach 2:
The patent segments the data processing function into independent modules (receiving PMA, symbol timing synchronization module, PCS) that all operate within the same clock domain. Each module processes data independently without requiring clock domain crossing, allowing parallel processing without latency overhead.
2Loss of time
If a device-wide clock drives all components, then clock domain crossings are eliminated reducing latency, but synchronization complexity with external serial data increases
Solution Approach 1:
The patent introduces a symbol timing synchronization module as an intermediary between the device-wide clock and the external serial data. This module uses a digital phase lock loop to detect synchronized bit values from the oversampled parallelized sample stream, acting as a mediator that translates external asynchronous data into the device's clock domain without adding latency.
Solution Approach 2:
The patent changes the sampling parameter by oversampling the serial data asynchronously at a higher rate. This allows the system to capture multiple samples per symbol period, providing more opportunities to identify the correct sampling phase and improving synchronization accuracy without requiring precise clock matching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces latency by eliminating clock domain crossings, allowing for immediate processing of serial data according to the device-wide clock timing, enhancing the network device's ability to handle high-speed data streams with reduced latency and increased accuracy in timestamping.
Implementation Method 1
The symbol timing synchronization module implements a digital phase lock loop to determine timing information for detecting the synchronized bit values from the parallelized sampled stream
Data Source
AI summary
A low-latency network device and method for treating serial data comprising an oscillator generating a device-wide clock; a receiving physical medium attachment (PMA) having an internal data width, a symbol timing synchronization module configured to receive the parallelized sample stream; and detect therefrom synchronized bit values corresponding to bit values of the received serial data; and a physical convergence sublayer (PCS). The PMA is configured to receive the serial data, deserialize the serial data based on the device-wide clock and internal data width, whereby the received serial data is oversampled, the oversampling of the received serial data being asynchronous relative to a timing of the received serial data, and output a parallelized sample stream. The PCS is configured to receive the synchronized bit values; and delineate packets therefrom to provide packet-delineated parallelized data. The PMA, the symbol timing synchronization module and the PCS are all driven by the device-wide clock.