Serial Data Reception Circuit for Multi-Block Pattern Detection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing receiving apparatuses struggle to correctly detect serial data containing multiple contiguous blocks with specific patterns and accurately determine bit errors across these blocks in high-speed serial communication systems.

Innovation Solution

A receiving apparatus comprising a serial-parallel conversion circuit, a register group, and a comparing circuit that generates N-bit wide parallel data, stores it in a register group, and compares it with M-bit known patterns to detect matches and bit errors across multiple contiguous blocks, using a detecting circuit to determine successful data reception based on specific timing and error tolerance criteria.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing receiving apparatuses use traditional pattern detection methods, then they can detect single block patterns, but they cannot correctly detect serial data containing multiple contiguous blocks with specific patterns

Engineering Contradiction:
Improvedetection accuracyVSAvoidmulti-block detection capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The detection process is segmented into multiple independent detection units, each responsible for detecting specific patterns in specific blocks. The detecting circuit includes multiple detection units that can independently detect patterns in different blocks simultaneously, enabling correct detection of serial data containing multiple contiguous blocks while maintaining high reliability.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If existing techniques detect bit errors in individual blocks, then they can determine errors in single blocks, but they cannot determine total bit errors in successive blocks

Engineering Contradiction:
Improvebit error measurementVSAvoidmulti-block error aggregation
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The detecting circuit merges the detection results from multiple detection units by aggregating bit error counts across all detected blocks. The circuit sums the bit errors from each block and compares the total against the allowable error threshold, enabling determination of total bit errors in successive blocks while maintaining precise measurement capability.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If the receiving apparatus performs successive detections in multiple blocks, then it can determine total bit errors, but the detection complexity increases

Engineering Contradiction:
Improvetotal error determinationVSAvoiddetection circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The detection units are designed with universal functionality to handle multiple blocks simultaneously. Each detection unit can detect patterns in any block and contribute to the total error count, allowing the system to achieve reliable total error determination while managing complexity through standardized, reusable detection components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8930802B2Receiving apparatus and method that detect reception of serial data having a plurality of blocks
Publication Date: 2015.01.06 MEGACHIPS
  • US8930802B2 patent drawing
  • US8930802B2 patent drawing
  • US8930802B2 patent drawing

AI summary

Exemplary receiving apparatus receives serial data that includes contiguous blocks each having M-bit known pattern. The apparatus includes a serial-parallel conversion circuit that arranges bits in the serial data to generates N-bit wide (N<M) parallel data, a register group including a first register that stores a word of the parallel data and second registers to which the word of the parallel data is sequentially shifted and stored, a comparing circuit that compares the known pattern with storage patterns each including M contiguous bits stored in the register group, and a detecting circuit. The detecting circuit detects reception of the serial data if the comparing circuit detects a first match between the known pattern and a first one of the storage patterns, and a second match between the known pattern and a second one of the storage patterns that starts with a specific bit during a specific clock cycle.