Serial Data Signal Synchronization via Oversampling and Filtering
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Solution Overview
Problem
Programmable logic devices (PLDs) face challenges in synchronizing high-speed serial data signals without a separate clock signal, as system skew and jitter exceed a quarter of a clock cycle at speeds above 200 Mbps, making data extraction difficult.
Innovation Solution
A method involving oversampling, filtering, and data extraction using a clock signal associated with the device, where samples are distributed over bit periods, and error correction is applied to extract data bit values without adjusting the clock frequency, utilizing sampling blocks, sample error filters, and data extraction blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If oversampling is used to synchronize serial data signals in PLDs, then data extraction can be performed with existing stable local clock, but system skew and jitter exceed 1/4 clock cycle at speeds above 200 Mbps making data extraction extremely difficult
Solution Approach 1:
The patent segments the synchronization process into multiple independent stages: oversampling the serial data signal to create multiple samples per bit period, filtering samples to identify valid data points, and extracting data bits from filtered samples. This segmentation allows each stage to handle specific aspects of the synchronization challenge, making the overall system more reliable despite high skew and jitter conditions.
Solution Approach 2:
The patent introduces an intermediary filtering stage between oversampling and data extraction. This filter acts as a mediator that processes the raw samples, corrects errors, and prepares cleaned data for extraction. The intermediary filter compensates for the adverse effects of skew and jitter, enabling accurate data extraction even when timing errors exceed 1/4 clock cycle.
2Reliability
If clock frequency is adjusted to synchronize with serial data signal, then proper synchronization can be achieved, but this approach is impractical to implement in PLDs including FPGAs or CPLDs
Solution Approach 1:
Instead of adjusting the clock frequency to match the serial data signal (conventional approach), the patent inverts the approach by keeping the stable local clock unchanged and adjusting the sampling strategy. Multiple samples are taken at different phases within each bit period, and the valid sample is identified through filtering. This inversion makes implementation feasible in PLDs while maintaining synchronization accuracy.
Solution Approach 2:
The patent changes the parameter being adjusted from clock frequency to sampling phase distribution. Rather than modifying the clock frequency to match the incoming data rate, the system maintains the stable local clock and distributes samples across multiple phases within each bit period. This parameter change enables practical implementation in PLDs while achieving proper synchronization.
3Productivity
If high speed serial data signals are received, then data transmission rate increases, but system skew and jitter increase making it extremely difficult to extract data
Solution Approach 1:
The patent applies periodic action by distributing multiple samples across different phases within each bit period. Instead of taking a single sample at a fixed phase, the system periodically samples the signal at multiple phase offsets (e.g., four samples per bit period). This periodic sampling strategy ensures that at least one sample falls within the valid data window even when skew and jitter are present, maintaining extraction accuracy at high speeds.
Solution Approach 2:
The patent implements feedback through the filtering stage that analyzes the distribution and quality of sampled points. The filter uses information from multiple samples to identify which samples contain valid data, correcting errors based on the pattern of sampled values. This feedback mechanism allows the system to adapt to varying skew and jitter conditions, maintaining accurate data extraction despite high transmission speeds.
Data Source
AI summary
Various techniques are provided for synchronizing serial data signals received by electronic systems or devices such as programmable logic devices (PLDs). In one example, a method of synchronizing data includes receiving a serial data signal at a device. The serial data signal operates independently of the device. The method also includes oversampling the serial data signal to provide a plurality of samples distributed over bit periods of the serial data signal. The method further includes filtering the samples to correct errors in the samples. In addition, the method includes extracting a plurality of data bit values from the samples under the control of a clock signal associated with the device without adjusting a frequency of the clock signal. Each data bit value is associated with one of the bit periods of the serial data signal.