Serial Data Stream Analysis via Virtual Clock Recovery
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Solution Overview
Problem
Traditional methods for acquiring and processing data signals in high-speed environments face challenges due to trigger jitter, which leads to synchronization issues and limitations in data analysis, and incur dead-time between acquisitions, preventing the analysis of contiguous data bits.
Innovation Solution
A method for capturing a long, continuous data stream and generating a synchronous virtual clock through clock recovery, using phase-locked-loop algorithms to synchronize sampling times, allowing for precise processing and elimination of trigger jitter, enabling accurate analysis of high-speed data signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional trigger-based acquisition method is used, then discrete data acquisitions can be obtained, but trigger jitter causes phase misalignment and synchronization issues
Solution Approach 1:
The patent extracts and removes the trigger signal from the acquisition system, transitioning to a continuous free-running acquisition mode where data is captured without trigger-based synchronization, thereby eliminating trigger jitter's impact on phase alignment
Solution Approach 2:
The patent creates a virtual clock signal that is derived from the recovered clock, which then serves as the timing reference for segmentation. This virtual clock copy replaces the original trigger signal's synchronization function without introducing jitter
2Speed
If high-speed clock signal is used for high-speed data acquisition, then acquisition speed increases, but clock jitter becomes a larger percentage of acquisition time
Solution Approach 1:
The patent creates a stable virtual clock by copying and processing the recovered clock signal through a software PLL, generating a jitter-free timing reference that maintains high-speed acquisition capability while eliminating clock jitter's impact on phase measurements
Solution Approach 2:
The patent replaces the hardware-based clock generation and distribution system with a software-based virtual clock system, eliminating the physical clock's jitter while maintaining the high-speed timing requirements through computational timing reference
3Productivity
If discrete acquisitions are performed with preparation time between them, then data can be processed and stored, but dead-time prevents analysis of contiguous data bits
Solution Approach 1:
The patent implements continuous free-running acquisition where data capture operates without interruption or dead-time, continuously acquiring all incoming data bits and enabling post-processing of contiguous data segments without gaps in the acquisition timeline
4Loss of information
If all data in a long continuous stream is captured, then complete data analysis is enabled, but data volume and processing complexity increase significantly
Solution Approach 1:
The patent segments the continuous data stream into discrete bit intervals using the virtual clock as timing reference, organizing the complete data stream into manageable, uniformly timed segments that can be processed independently while maintaining overall data completeness
Solution Approach 2:
The patent performs preliminary segmentation and organization of the continuous data stream into uniformly timed bit intervals before detailed analysis, preparing the data in advance with proper timing markers and structure to simplify subsequent processing steps
Data Source
AI summary
A method of processing a data signal is provided. The method comprises the steps of acquiring a data signal by an acquisition unit of a test instrument for a predetermined time and storing the data signal in a memory of the test instrument. A clock signal is recovered from the stored data signal, and the stored data signal is sliced into a plurality of data segments of a predetermined length in accordance with the recovered clock signal.