Multi-Lane Serial Interface De-Skew Clock Calibration
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Solution Overview
Problem
Conventional methodologies for serial channel initialization in fully-buffered dual in-line memory modules (FB-DIMM) are complex and can introduce latency in data transport across the serial channel.
Innovation Solution
A method for clock calibration and de-skew on a multi-lane high-speed serial interface, involving the reception of data frames with training sequence headers, generation of event signals, and alignment of the core clock with the slowest bit lane to optimize data transport.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methodologies for serial channel initialization are used, then the initialization process can be completed, but the process becomes complicated and introduces latency to data transport
Solution Approach 1:
The patent performs de-skew calibration during the initialization phase by detecting training sequence headers and measuring arrival time differences across lanes. This preliminary action establishes the correct clock phase relationship before actual data transport begins, preventing latency issues during normal operation. The system captures the relative timing of training sequences from each lane and adjusts the clock phase accordingly before production data transmission starts.
2Reliability
If conventional serial channel initialization is performed, then channel setup is achieved, but the complexity of the initialization process increases
Solution Approach 1:
The system performs self-calibration by automatically detecting training sequence headers transmitted during initialization and autonomously measuring the arrival time differences across lanes. The AMB (Arbiter Memory Buffer) self-determines the de-skew values and adjusts its internal clock phases without external intervention. This self-service approach simplifies the overall initialization process by eliminating the need for complex external calibration equipment or manual configuration.
Solution Approach 2:
The patent implements a feedback mechanism where the system detects training sequence headers from each lane, measures their arrival times, and uses this information to adjust the clock phase for each lane. The measured timing differences feed back into the de-skew calibration process, allowing the system to iteratively refine the clock synchronization until optimal alignment is achieved across all lanes.
3Productivity
If clock alignment is performed without considering lane skew, then initialization is faster, but data transmission accuracy deteriorates
Solution Approach 1:
The system performs de-skew calibration as a preliminary step during initialization by detecting training sequence headers and measuring lane arrival time differences. This preliminary measurement and adjustment of clock phases ensures that when actual data transmission begins, all lanes are properly synchronized, maintaining high data transmission accuracy without sacrificing initialization speed.
Data Source
AI summary
A method and system for performing clock calibration and de-skew on a multi-lane high speed serial interface is presented. Each of a plurality of serial lane transceivers associated with an individual bit lane receives a first data frame, comprising a training sequence header pattern. Based on each of the first data frames, the plurality of serial lane transceivers de-skew a plurality of data frames and generate a plurality of event signals. Using the plurality of event signals, a core clock, having a first phase, is adjusted to be phase aligned with the slowest bit lane.