Serial Differential Cell Using Delayed Outputs for Low-Power High-Speed Links
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Solution Overview
Problem
Circuits supporting high-speed data transfer rates, such as USB 3.0, often require high power, which hinders their implementation in low-power applications.
Innovation Solution
A device and method that serialize and delay parallel input data signals to produce serial differential output signals, operating at a clock rate half that of the data rate, effectively reducing power requirements while maintaining high-speed data transfer capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If circuits are designed to support high-speed data transfer rates (e.g., USB 3.0 at 5 Gbps), then data transfer speed is improved, but power consumption increases significantly
Solution Approach 1:
The circuit is divided into multiple independent cells, each handling a portion of the data serialization task. Each cell processes parallel input signals independently and generates differential output signals, allowing the system to achieve high-speed data transfer while distributing power consumption across multiple smaller units rather than requiring a single high-power circuit
Solution Approach 2:
The circuit operates using clocked periodic action where parallel input signals are serialized in synchronized cycles. By using a clock signal to periodically latch and transfer data through the cell stages, the circuit achieves high-speed serial data transfer at 5 Gbps while maintaining low power consumption through efficient clocked operation rather than continuous high-power signal processing
2Productivity
If parallel single-ended signals are converted to serial differential signals for high-speed transfer, then data transfer capability is improved, but circuit complexity increases
Solution Approach 1:
The complex signal conversion function is segmented into multiple identical cells working in parallel. Each cell handles a specific portion of the parallel-to-serial conversion, transforming N parallel single-ended inputs into N/2 serial differential outputs. This segmentation makes the overall complex function manageable through repeated modular units
Solution Approach 2:
The patent uses identical copies of the same cell structure to perform the signal conversion. Each cell is a replicated unit with the same logic and configuration, processing its portion of the input signals in the same manner. This copying approach simplifies design and verification while achieving the required data transfer capability through parallel operation of multiple identical units
Data Source
AI summary
Techniques are provided to serialize and delay parallel input data signals and are particularly useful for low power applications. In one example, a device includes a plurality of data input ports adapted to receive N parallel single-ended input data signals, and a clock input port adapted to receive a clock signal substantially synchronized with the parallel single-ended input data signals. The device also includes a cell adapted to serialize the parallel single-ended input data signals to provide N/2 first serial differential output data signals in response to the clock signal, delay the parallel single-ended input data signals, and serialize the delayed parallel single-ended input data signals to provide N/2 delayed second serial differential output data signals in response to the clock signal. The delayed second serial differential output data signals are delayed relative to the first serial differential output data signals. The device also includes a plurality of output ports.