Serial Direct Access Circuit for Memory Testing Efficiency
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Solution Overview
Problem
The existing parallel interface in integrated circuits makes it difficult and costly to perform function tests, as each pin needs to be connected to a pad, limiting the efficiency of testing and requiring extensive layout area, and constraining the number of dice that can be tested simultaneously.
Innovation Solution
A serial direct access (SDA) circuit with an enable pin, serial pin, and auto-test module that allows selective enabling and disabling for built-in testing, enabling serial access and reducing the number of pads needed for probing, thereby improving testing efficiency and supporting multi-die testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a parallel interface with multiple pins is used for memory communication, then communication efficiency is improved, but testing complexity and cost increase significantly
Solution Approach 1:
The patent changes the interface parameter from parallel to serial, transforming the testing approach from requiring multiple simultaneous probe connections to using a single serial connection. This parameter change resolves the contradiction by maintaining memory access capability while dramatically simplifying the testing infrastructure required.
Solution Approach 2:
The patent introduces a serial direct access (SDA) circuit as an intermediary component that bridges the external tester and the memory's parallel interface. This mediator converts serial test signals into parallel memory access signals, allowing complex parallel memory operations to be controlled through a simple serial interface, thus reducing testing complexity.
2Reliability
If each pin of the parallel interface is connected to an individual pad for testing, then complete function test is enabled, but layout area occupied increases significantly
Solution Approach 1:
The patent merges multiple pad requirements into a single pad by implementing a serial interface that consolidates what would otherwise require multiple separate pad connections. The SDA circuit receives serial data through one pad and internally generates the necessary parallel signals, eliminating the need for multiple individual pad connections while maintaining complete testing capability.
3Reliability
If multiple pads are required for probing parallel pins, then comprehensive testing is possible, but the number of dice that can be tested simultaneously by a single probing card decreases
Solution Approach 1:
The patent makes the single serial pad universal by designing it to handle multiple functions: address input, data input, control signaling, and test operations. This multi-functional serial interface allows a single pad connection to replace what would otherwise require multiple dedicated pads, thereby increasing the number of dice that can be tested in parallel by a single probing card while maintaining comprehensive testing capability.
4Area of stationary object
If a serial interface is implemented for direct access, then the number of pads needed is reduced, but additional control logic is required
Solution Approach 1:
The patent transitions from a spatial parallel interface to a temporal serial interface, changing the dimension of data transmission from simultaneous multi-pin signaling to sequential single-pin signaling. This dimensional change reduces the spatial requirement (number of pads) while the control logic complexity is managed through structured state machine implementation within the SDA circuit, achieving an acceptable trade-off.
Data Source
AI summary
The present invention provides a memory architecture and associated serial direct access (SDA) circuit. The memory architecture includes a memory of a parallel interface and a serial direct access (SDA) circuit. The SDA circuit includes an enable pin, a serial pin and an auto-test module. The enable pin receives an enable bit, wherein the SDA circuit is selectively enabled and disabled in response to the enable bit. When the SDA circuit is enabled, the serial pin sequentially relaying a plurality of serial bits, such that each of the serial bits is associated with one of parallel pins of the parallel interface; in addition, the auto-test module can perform a built-in test of the memory associated with the serial bits.