Transmission-Gate Dispatcher for High-Speed Serial Jitter Tolerance
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Solution Overview
Problem
Existing dispatcher technologies for high-speed serial data streams face challenges such as high input load, large area requirements, high power consumption, and low jitter tolerance due to the use of flip-flops and complex wire routing, making them unsuitable for efficient processing of high-speed data.
Innovation Solution
The proposed solution involves a multiplexer and demultiplexer arrangement using transmission gates with a controller to process high-speed serial data streams, allowing for efficient data separation and parallel output with reduced power consumption and increased jitter tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If flip-flops are used for dispatching high-speed serial data streams, then data can be dispatched, but the input load increases with n channels causing large input delay
Solution Approach 1:
The patent replaces the mechanical/electrical flip-flop based switching mechanism with an optical-based solution using optical modulators and optical switches. This substitution eliminates the electrical input load constraints and allows for scaling to many channels without proportionally increasing the input delay, as optical signals can be switched at high speeds with minimal delay.
Solution Approach 2:
The patent introduces an optical dimension to the data dispatching system by converting electrical signals to optical signals for transmission and switching, then converting back to electrical signals at the output. This dimensional change allows the system to bypass the limitations of electrical switching and achieve lower input delay and higher scalability.
2Productivity
If flip-flops are used in dispatcher arrangement, then data dispatching is achieved, but area required is relatively high and proportional to n
Solution Approach 1:
The patent merges multiple data channels into a single optical transmission medium using wavelength division multiplexing or time division multiplexing, then uses a single optical switch or a small number of optical switches to route the combined signal to multiple output channels. This merging approach dramatically reduces the number of individual switching elements required compared to having separate flip-flops for each channel.
Solution Approach 2:
The optical switching infrastructure is designed to be universal and multi-functional, where the same optical switch can handle multiple channels by dynamically configuring its routing based on the input signal characteristics. This universal approach allows a single component to perform the function of what would otherwise require multiple dedicated components.
3Productivity
If flip-flops with high static power consumption are used, then data can be dispatched, but power consumption is high
Solution Approach 1:
The patent replaces the electrical flip-flop based switching mechanism with an optical-based solution using optical modulators and optical switches. This substitution eliminates the electrical input load constraints and allows for scaling to many channels without proportionally increasing the input delay, as optical signals can be switched at high speeds with minimal delay.
4Productivity
If conventional dispatcher arrangements are used, then data dispatching is achieved, but jitter tolerance is low
Solution Approach 1:
The patent replaces the electrical switching mechanism with optical switching, which has inherently lower jitter characteristics. Optical switches can respond to control signals with minimal delay variation, and the optical transmission medium preserves signal integrity better than electrical transmission, resulting in higher jitter tolerance while maintaining high data dispatching speeds.
Data Source
AI summary
A deserializer circuit includes demultiplexer circuitry configured to receive serial data from an input and output a plurality of divided data outputs, and multiplexer circuitry configured to receive a first logic level at a first input of said multiplexer circuitry, and receive a second logic level at a second input of said multiplexer circuitry and receive one of said divided data outputs at a control input of said multiplexer circuitry. The outputs of the multiplexer circuitry produce the received serial data in a parallel form.