Serial Division Circuitry for Crest Factor Reduction Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing crest factor reduction (CFR) techniques for power amplifiers in communication systems are resource-intensive, particularly in integrated circuit devices with limited hardware resources, due to the need for extensive circuitry like divider circuits to calculate scaling factors for peak cancellation.
Innovation Solution
A method and circuitry that perform serial division operations to generate scaling factors with reduced resource usage, allowing for efficient peak detection and division operations, and reinitializing division based on newly identified signal peaks to optimize resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional divider circuits are used to calculate scaling factors for peak cancellation, then accurate scaling factors can be obtained, but the hardware resource consumption increases significantly
Solution Approach 1:
The patent replaces complex, resource-intensive divider circuits with a simpler serial division implementation that uses basic logic operations (AND, OR, NOT gates) to achieve division functionality. This approach uses cheaper, less resource-consuming circuit elements that can be disposed of or reconfigured more easily, significantly reducing hardware resource consumption while maintaining the necessary calculation accuracy for scaling factors
Solution Approach 2:
The patent substitutes traditional mechanical/divider circuit-based division operations with a logical/mathematical approach using bit-wise operations and serial processing. Instead of relying on physical divider circuits, the system uses logical operations to perform division, replacing a mechanical/electrical system with a logical computation system that consumes fewer hardware resources
2Speed
If multiple divider circuits are implemented to handle parallel peak detection and division operations, then processing speed increases, but the number of hardware resources required increases
Solution Approach 1:
The patent segments the division operation into serial bit-wise steps, processing one bit at a time through multiple clock cycles. This allows a single divider circuit to handle multiple division operations sequentially, eliminating the need for multiple parallel divider circuits. The segmentation of the division process into manageable bit-level operations enables time-parallel processing while using space-serial hardware resources
Solution Approach 2:
The patent implements periodic clock signals to control the serial division process, where each clock cycle performs a single bit of division operation. This periodic action allows the system to process multiple peaks in sequence using a single divider circuit, achieving the necessary processing throughput without requiring multiple simultaneous divider circuits. The periodic clocking enables systematic progression through the serial division steps
3Device complexity
If serial division operations are used instead of parallel divider circuits, then hardware resource consumption decreases, but the calculation time for each scaling factor increases
Solution Approach 1:
The patent maintains continuous useful action by overlapping the serial division operation with peak detection activities. While one division operation is proceeding serially, the system continues to detect new peaks in the input signal. This continuous operation ensures that when a new peak is detected, the system is already prepared or can quickly transition to processing it, minimizing idle time and maintaining productive workflow despite the serial nature of the division operation
Solution Approach 2:
The patent performs preliminary peak detection and preparation before the serial division operation completes. By detecting peaks in advance and preparing the division process, the system minimizes the effective calculation time impact. The serial division is initiated as soon as a peak is identified, and the system continues detecting subsequent peaks, so the perceived delay is reduced by the overlap of preparation and execution phases
Data Source
AI summary
A method includes identifying a signal peak from an input signal. The signal peak may be detected with peak detection circuitry. A serial division operation may be performed on the identified signal peak value with serial division circuitry to obtain a scaling factor. The peak detection circuitry may identify an additional signal peak from the input signal concurrently with the serial division operation. The serial division operation may be halted if the additional identified signal peak is greater than the previous identified signal peak. Another serial division operation may be performed based on the additional identified signal peak.