Serial Communication Duty Cycle Extension Circuit
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Solution Overview
Problem
Multi-chip serial communication systems face performance limitations due to increased data transmission and speed requirements, primarily restricted by the deterioration of the duty cycle of communication signals as the number of chips connected in series increases.
Innovation Solution
A computing device with multiple computing modules connected via serial communication paths, each equipped with an internal circuit for signal processing and an extension circuit that includes delay units and logic gates to selectively perform level extension on signals, thereby adjusting the duty cycle and improving communication efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of chips connected in series is increased to improve processing capability, then the computing power and data transmission capacity are improved, but the duty cycle of communication signals deteriorates and communication reliability decreases
Solution Approach 1:
The patent changes the temporal parameters of the communication signal by introducing delay units that extend the pulse width. This parameter transformation converts a narrow pulse signal into a widened pulse signal, allowing the signal to maintain sufficient duty cycle even after multiple serial transmissions through multiple chips, thereby resolving the duty cycle deterioration problem while maintaining system productivity
Solution Approach 2:
The extension circuit acts as an intermediary component between the internal circuit and the serial communication path. It receives the original signal, processes it through delay units to extend the pulse width, and outputs the extended signal. This intermediary mechanism protects the communication reliability by ensuring the signal maintains adequate duty cycle characteristics throughout the serial communication chain
2Speed
If the speed requirement for serial communication is increased to meet performance demands, then the data transmission speed is improved, but the duty cycle deterioration occurs more rapidly
Solution Approach 1:
The extension circuit performs preliminary action by extending the pulse width of the signal before it enters the serial communication path. This advance processing ensures that even when the signal undergoes multiple transmissions at high speeds, the duty cycle remains sufficient. The delay units are configured to provide the necessary pulse width extension in advance, compensating for the cumulative duty cycle loss that would occur during high-speed serial transmission
Data Source
AI summary
A computing device and a computing system are provided. The computing device comprises: a plurality of computing modules; and serial communication paths between/among the plurality of computing modules. Each computing module comprises: an internal circuit for performing an operation on a signal received from a corresponding serial communication path; and an extension circuit for receiving a signal from the internal circuit as an input signal. The extension circuit comprises: a delay module for delaying the input signal, the delay module comprising one or more delay units; one or more extension select modules for selectively performing a level extension on the input signal through the signal delayed by corresponding one or more delay units to generate one or more respective level-extended signals; and an output module for outputting one or more of the one or more level-extended signals.