Serial Protocol Switched Fabric for Computing Backplane Congestion
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Solution Overview
Problem
Current computer architectures face a bandwidth bottleneck due to the divergence between processor speeds and memory access speeds, leading to inefficiencies in data transfer and throughput, particularly exacerbated by limitations in parallel bus technologies and the need for scalable solutions that match increasing processor and memory speeds.
Innovation Solution
A computing and communication architecture utilizing a serial protocol-based switched fabric among circuit cards, with each card equipped with a protocol processor for packet-based self-clocked communications, eliminating the need for hierarchical arrangements and addressing switch blocking and congestion issues, thereby enabling efficient high-speed data transfer between processors and memory across multiple cards and shelves.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If parallel bus technologies are used for interconnection, then device compatibility and ease of manufacture are improved, but bandwidth and data transfer speed deteriorate due to inherent limitations in parallel bus architecture
Solution Approach 1:
The patent replaces parallel bus mechanical interconnection with a protocol translation architecture that uses serial communication interfaces. The parallel bus interface circuit converts parallel data from legacy components into serial packets for transmission over high-speed serial links, eliminating the bandwidth limitations of parallel bus architecture while maintaining compatibility with existing parallel components.
Solution Approach 2:
The invention changes the fundamental communication parameter from parallel to serial transmission. By translating parallel bus signals into serial packet format and using protocol translation circuits, the system achieves higher data transfer speeds while maintaining backward compatibility with parallel bus devices through parameter transformation rather than direct parallel link extension.
2Productivity
If processor speed is increased to improve computing performance, then productivity is improved, but bandwidth bottleneck worsens due to divergence between processor speed and memory access speed
Solution Approach 1:
The patent introduces protocol translation circuits and packet switching fabric as intermediary components between the processor and memory subsystem. These intermediaries buffer, translate, and route data packets efficiently, decoupling the high-speed processor from the relatively slower memory access and eliminating the direct bandwidth bottleneck that exists in traditional tightly-coupled architectures.
Solution Approach 2:
The system segments the data transfer path into discrete packetized units that can be independently routed through the switched fabric. This segmentation allows multiple simultaneous data streams to traverse the interconnection network without contention, effectively increasing aggregate bandwidth between processor and memory compared to traditional shared bus architectures.
3Device complexity
If hierarchical packaging arrangement is used for circuit cards, then device complexity is reduced, but switch blocking and congestion issues worsen due to traffic bottlenecks at hierarchy levels
Solution Approach 1:
The patent implements a universal protocol translation capability that enables any circuit card to communicate with any other card through a common packet-switched fabric. Rather than requiring hierarchical arrangements with specialized interconnects for different card types, the system provides a flat, universal communication medium where all cards have equal access, eliminating hierarchy-induced blocking while maintaining manageable complexity through standardization.
Data Source
AI summary
A computing and communication architecture utilizes a serial protocol based switched fabric among circuit cards housed in packaging arrangement. In one embodiment, each circuit card connected to the serial protocol based switched fabric in the packaging arrangement is provided with a protocol processor that enables all of the circuit cards to efficiently provide packet-based serial self-clocked communications at line speed. As a result, it is not necessary to arrange the circuit cards in a hierarchical manner in order to address the problems of switch blocking and related traffic congestion issues that would otherwise limit the implementation of the serial protocol based backplane arrangement for housing circuit cards.