Serial Flash Memory Core with Shared Page Buffers for High Throughput
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Solution Overview
Problem
Current Flash memory technologies face limitations in data throughput and signal quality due to the use of parallel data interfaces, which suffer from issues like cross-talk and signal attenuation when operated beyond their rated frequencies, and the push for increased memory density complicates sensing data from NAND cell strings, leading to decreased cell current and yield.
Innovation Solution
A memory system with a serial data interface and a serial data path core that divides the memory bank into two halves, each with a shared two-dimensional page buffer and integrated self-column decoding, minimizing circuit and chip area overhead, and allowing direct data transfer between memory banks without external routing, thereby enhancing data throughput and reducing physical constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased to achieve higher storage capacity, then storage density is improved, but sensing speed and data throughput deteriorate due to signal degradation
Solution Approach 1:
The memory array is divided into multiple sectors, with each sector having its own dedicated page buffer. This segmentation allows parallel sensing operations across multiple sectors, thereby maintaining high sensing speed even as overall memory density increases. The sectorized architecture prevents signal degradation from bottlenecking the entire system.
Solution Approach 2:
The patent transitions from a traditional parallel data interface to a serial data interface for the core memory array. This dimensional change in data transfer methodology enables higher operating frequencies (up to 200 MHz) and improves data throughput while working around the signal degradation issues inherent in high-density parallel interfaces.
2Productivity
If parallel data interface is used to achieve high data throughput, then data transfer speed is improved, but signal quality deteriorates due to cross-talk, signal skew and attenuation
Solution Approach 1:
Instead of using a parallel interface (multiple simultaneous signal lines), the patent inverts the approach by using a serial interface (single sequential signal line). This inversion eliminates cross-talk and signal skew issues inherent in parallel interfaces, as only one signal is transmitted at a time, while still achieving high throughput through increased operating frequency.
Solution Approach 2:
The patent replaces the mechanical/electrical parallel bus structure with a serial communication protocol. This substitution transforms the data transfer mechanism from simultaneous multi-signal transmission to sequential single-signal transmission, thereby eliminating electromagnetic interference issues while maintaining high data rates through frequency optimization.
3Speed
If dedicated page buffers are allocated to each memory sector, then sensing speed is improved, but chip area consumption increases
Solution Approach 1:
The patent merges the column decoding functionality into the page buffer circuit itself, creating an integrated self-decoding page buffer. This consolidation eliminates the need for separate column decoding circuits for each sector, thereby maintaining parallel sensing capability while significantly reducing the total chip area required for buffer circuits.
Solution Approach 2:
Each page buffer is designed with multi-functionality, serving both as a data buffer and as a column decoder. This universal design allows a single circuit to perform multiple functions that would traditionally require separate dedicated circuits, thereby reducing overall chip area while maintaining sensing speed through parallel operation.
Data Source
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AI summary
A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.