Serial Flash Memory Extended Address Register 32Gb Capacity
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Solution Overview
Problem
The limited addressability and storage capacity of typical serial flash memory devices restrict their application in execute-in-place (XiP) implementations and other applications, as they can only address a maximum of 16M storage locations using a 24-bit address, which is insufficient for larger memory spaces.
Innovation Solution
The implementation of an extended address register that combines with the conventional 24-bit address to create a 32-bit address, allowing access to greater than 16M storage locations without modifying the standard Serial Peripheral Interconnect (SPI) protocol, thereby enhancing addressability and storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a 24-bit address is used in serial flash memory devices, then the device maintains compatibility with the standard SPI protocol, but the addressable storage capacity is limited to 16M locations
Solution Approach 1:
The address space is segmented into two parts: an extended address (EA) that identifies a subset of storage locations, and a conventional 24-bit address that identifies a specific location within that subset. This segmentation allows the memory device to address more than 16M locations while maintaining compatibility with the standard SPI protocol for the lower address bits.
Solution Approach 2:
The patent adds another dimension to the addressing scheme by introducing the extended address field. Instead of relying solely on the 24-bit address width, the system now uses a hierarchical addressing structure where the EA selects a bank or subset, and the 24-bit address selects within that subset, effectively creating a 2D address space that exceeds the original 16M limitation.
2Quantity of substance
If the addressable storage capacity is increased beyond 16M locations, then larger memory spaces become accessible, but compatibility with the standard SPI protocol is compromised
Solution Approach 1:
The extended address is loaded into an extended address register in advance before the actual memory access operation. This preliminary action allows the memory device to prepare the upper address bits separately, then combine them with the standard 24-bit address during the SPI transaction, maintaining protocol compatibility while enabling access to larger memory spaces.
Solution Approach 2:
The extended address register acts as an intermediary between the standard SPI interface and the larger address space. It holds the extended address bits and combines them with the 24-bit address from the SPI protocol, serving as a buffer that reconciles the limitation of the standard protocol with the need for larger addressable space.
Data Source
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AI summary
Example embodiments for providing enhanced addressability for a serial non¬ volatile memory device may comprise accessing a storage location based, at least in part, on an extended address value and an address, the extended address value to identify a subset of storage locations from a plurality of storage locations, the address to identify the storage location within the subset of storage locations.