Serial Fuse Array Layout Using D Flip-Flop Chains
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Solution Overview
Problem
As semiconductor memory devices shrink in size, the increasing number of signal lines required to connect fuses outside the memory cell complicates the layout design and increases the occupied area, making it difficult to manage the layout effectively.
Innovation Solution
A fuse array that transmits signals through D flip-flops connected in series, where each fuse is coupled with a corresponding D flip-flop to receive and transmit clock and data signals, reducing the number of necessary signal lines by using a single data line and clock line for multiple fuses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If fuses are located outside the memory cell to save space, then the memory cell area is reduced, but the number of signal lines increases and occupies greater layout area
Solution Approach 1:
Multiple fuses share common signal transmission paths through the series-connected D flip-flop chain. Instead of dedicating separate signal lines to each fuse, the invention merges the signal transmission function into a single serial data line that carries information from all fuses sequentially, dramatically reducing the number of required signal lines
Solution Approach 2:
The invention transforms the signal transmission from a parallel structure (one line per fuse) to a serial structure (single line carrying sequential data). By adding the time dimension through clocked serial transmission, the spatial complexity of signal lines is reduced while maintaining the ability to address and read individual fuse states
2Adaptability or versatility
If more fuses are allocated to handle more signals, then the repair capability is improved, but the number of signal lines increases and layout difficulty increases
Solution Approach 1:
The invention changes the signal transmission parameter from parallel to serial mode. By using a single data line with sequential clocked transmission, the system can accommodate any number of fuses without proportionally increasing the number of signal lines. The serial transmission parameter allows scalable fuse arrays while maintaining constant signal line count
Solution Approach 2:
The series-connected D flip-flop chain serves multiple functions: it acts as a shift register for serial data transmission, a temporary storage element for fuse states, and a interface between the fuse array and control logic. This multi-functional design eliminates the need for separate dedicated signal lines for each fuse
Data Source
AI summary
A fuse array and a memory device are provided in the invention. The fuse array includes a plurality of fuses and a plurality of first D flip-flops. The fuses are configured to generate a plurality of data signals. Each of the first D flip-flops is respectively coupled to one corresponding fuse of the fuses to receive the data signal from the corresponding fuse and the first D flip-flops transmit a clock signal and the data signal to a plurality of second D flip-flops comprised in a plurality of memory cells. The first D flip-flops are connected in series and the second D flip-flops are connected in series.