Serial Image Processing Units for PCIe Switch Bottleneck

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Solution Overview

Problem

Existing image processing systems face performance bottlenecks due to the limitations of bus transfer speeds when connecting multiple image processing units, leading to complex data division and coupling methods, especially as the number of processing modules increases.

Innovation Solution

The system configures multiple image processing units in a serial connection, where each unit transfers data without modification to the next unit, allowing for efficient parallel processing and reducing the need for a PCIe switch with multiple ports, thereby simplifying the circuit scale and terminal count.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple image processing units are connected via bus to improve processing performance, then processing speed is improved, but bus transfer performance becomes a bottleneck

Engineering Contradiction:
Improveprocessing speedVSAvoidbus transfer performance bottleneck
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent divides the image processing system into multiple independent image processing units, each capable of autonomous parallel processing. By segmenting the processing workload across multiple units connected via PCIe switches rather than a shared bus, the system eliminates the bus transfer bottleneck while maintaining improved processing speed through parallel operation of discrete processing segments.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the number of image processing modules is increased to improve processing performance, then processing capability is improved, but the number of PCIe switch ports and circuit scale increase proportionally

Engineering Contradiction:
Improveprocessing capabilityVSAvoidcircuit scale and terminal count
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent transitions from a one-dimensional bus connection model to a multi-dimensional PCIe switch network architecture. This dimensional change allows multiple image processing units to be connected through hierarchical or mesh-like PCIe switch configurations, enabling processing capability to scale without linearly increasing the number of ports per switch, thus reducing overall circuit scale and terminal count.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If image data is divided in the main scanning direction using multiple image processing modules, then parallel processing is achieved, but data division and coupling methods become complicated

Engineering Contradiction:
Improveparallel processing efficiencyVSAvoiddata division and coupling complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent inverts the traditional approach by having multiple image processing units process different color components (e.g., different color planes or color spaces) simultaneously rather than dividing the same image data across multiple units. This inversion simplifies data division and coupling since each unit receives independent color data that can be processed in parallel and then combined, eliminating complex data shuffling and synchronization requirements.

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentUS9953251B2Image processing apparatus and image processing method for executing image processing using multiple serial image processing units to process different colors
Publication Date: 2018.04.24 CANON KK
  • US9953251B2 patent drawing
  • US9953251B2 patent drawing
  • US9953251B2 patent drawing

AI summary

An apparatus includes multiple image processing units configured to execute image processing on input data, which are connected in serial, and include two or more image processing units having the same image processing function. The image processing units include a transfer unit configured to transfer input first data to a next image processing unit without changing the data, and an image processor configured to execute image processing on the first data to output second data. At least one of the image processing units transfers the first data to the next image processing unit without changing the first data when the first data is input, and also outputs the second data.