Serial Interconnect for High Bandwidth Low Power ICs

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Solution Overview

Problem

Existing interconnect technologies for integrated circuits, such as AXI interconnects, face challenges in increasing bandwidth while reducing power and area overhead, and pin-count, particularly due to the need for wide datawidths which increase gate count and latency, and are unsuitable for efficient use with the AXI protocol.

Innovation Solution

The technology employs serializing and deserializing circuits to convert parallel signals to serial streams and back, allowing for mixed interconnect mechanisms, reducing signal count, and using techniques like short codes, differential signaling, and Manchester encoding to improve efficiency and transparency, while maintaining high bandwidth and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the data path width is increased to increase bandwidth capability, then the bandwidth capability is improved, but the gate count increases leading to increased power consumption and reduced timing performance

Engineering Contradiction:

Improvebandwidth capabilityVSAvoidgate count

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent replaces the traditional parallel mechanical signal transmission system with a serial transmission system. Instead of using wide parallel data paths that require numerous simultaneous signal lines and associated gating, the invention uses serial transmission where data is transmitted bit-by-bit or byte-by-byte through a narrow data path, fundamentally changing the transmission mechanism from parallel to serial

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent transitions from a spatial dimension approach (wide parallel data paths requiring more physical signal lines) to a temporal dimension approach (serial transmission over time). Data that would traditionally be transmitted simultaneously across multiple parallel lines is instead transmitted sequentially over a single or few serial lines, adding the time dimension to the transmission process

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If the data path width is increased to increase bandwidth capability, then the bandwidth capability is improved, but the timing performance deteriorates

Engineering Contradiction:

Improvebandwidth capabilityVSAvoidtiming performance

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent replaces the parallel signal transmission mechanism with serial transmission, eliminating the need for simultaneous arrival of multiple wide data path signals. This substitution allows for easier timing control and synchronization since serial data can be clocked in sequentially without the complex timing skew issues inherent in wide parallel buses

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Productivity

If the data path width is increased to increase bandwidth capability, then the bandwidth capability is improved, but the power consumption increases

Engineering Contradiction:

Improvebandwidth capabilityVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent replaces the high-power parallel transmission system with a low-power serial transmission system. By transmitting data sequentially rather than simultaneously across multiple wide signal lines, the total switching activity and associated dynamic power consumption is dramatically reduced, even though the same amount of data is transmitted

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Productivity

If the data path width is increased to increase bandwidth capability, then the bandwidth capability is improved, but the silicon surface area increases

Engineering Contradiction:

Improvebandwidth capabilityVSAvoidsilicon surface area

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The patent replaces the area-intensive parallel data path implementation with a compact serial transmission implementation. Instead of routing numerous wide parallel signal lines across the chip requiring significant silicon real estate, the serial implementation uses a narrow data path that occupies minimal surface area while achieving comparable or superior effective bandwidth through efficient serialization

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

5Productivity

If the data path width is increased to increase bandwidth capability, then the bandwidth capability is improved, but the number of signals to route and connect increases

Engineering Contradiction:

Improvebandwidth capabilityVSAvoidsignal count

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent replaces the complex parallel signal routing system with a simple serial transmission system. Instead of designing and routing numerous parallel signal lines and their associated control, clock, and data signals, the serial implementation reduces the signal count to a minimal set required for sequential data transmission, dramatically simplifying the routing complexity

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS8006008B2Apparatus and method for data processing having an on-chip or off-chip interconnect between two or more devices

Publication Date: 2011.08.23 ARM LTD

AI summary

A data processing apparatus is provided with multiple devices. These devices generate parallel signals using a parallel signal protocol. A serializing circuit captures a set of parallel signals, serializes them to form a serial stream of data and transmits this serial stream of data. A deserializing circuit at a destination device receives this serial stream of data, deserializes this serial stream of data to form a second set of parallel signals corresponding to the first set of parallel signals and then applies this second set of parallel signals to the destination device.