Serial Interface Address Caching for Image Forming Apparatus
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In digital multifunction peripherals, the processing speed is reduced due to the need for serial communication with a storage circuit having a transitory memory for buffering between the image generating and image forming units, leading to inefficiencies in high-speed printing operations.
Innovation Solution
Implementing a serial interface that omits storing partial information of addresses if they match previous addresses, thereby reducing communication volume and maintaining processing speed during high-speed printing by efficiently writing settings to the transitory storage circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If serial communication is used to access the storage circuit's registers for setting, then the device complexity is reduced and ease of operation is improved, but the processing speed is reduced due to the time required for serial communication
Solution Approach 1:
The patent applies preliminary action by performing register setting operations in advance before image data transfer begins. The controller completes all necessary register configurations for the storage circuit prior to initiating data transfer, ensuring that no setting operations are needed during the critical data transfer period. This separation of setup and execution phases eliminates communication delays during processing.
Solution Approach 2:
The patent ensures continuity of useful action by maintaining uninterrupted image data transfer between the controller and storage circuit. By completing all register settings beforehand and using a FIFO-based storage circuit that requires no mid-transfer configuration, the system achieves continuous data flow without pauses for communication, maximizing processing speed.
2Reliability
If the storage circuit is configured to buffer image data between controller and printer engine, then the reliability of real-time processing is improved, but the loss of time occurs due to serial communication overhead for register access
Solution Approach 1:
The controller performs all register setting operations for the storage circuit in advance, before image data transfer begins. This preliminary configuration ensures the storage circuit is properly prepared for buffering operations while eliminating time-consuming communication during the actual data transfer process.
Solution Approach 2:
The patent skips unnecessary communication steps by implementing a storage circuit with a FIFO buffer that automatically manages data flow without requiring repeated register access during transfer. The system rushes through the data transfer process at high speed by eliminating intermediate communication interruptions.
3Productivity
If multiple sheets of image data are printed sequentially, then the productivity is improved, but the loss of time occurs because setting the storage circuit for the next page must be completed while current image data is transferred
Solution Approach 1:
The controller completes all register settings for the storage circuit in advance before data transfer begins. This preliminary action allows the system to prepare for multiple pages of image data without interruption, as no setting operations are needed during the transfer of current or subsequent pages.
Solution Approach 2:
The FIFO-based storage circuit enables continuous data transfer for multiple pages without pausing for reconfiguration. The circuit maintains uninterrupted buffer operations across page boundaries, allowing the controller to continuously feed image data for multiple sheets without time loss from setting operations.
Data Source
AI summary
A communication I/F of an image generating unit writes settings for an image data to a transitory storage unit by serial communication before the image data is transmitted from the image generating unit to the transitory storage unit. The communication I/F stores partial information of an address used for previous writing in a cache unit, and omits the writing of the partial information of the address used for further writing if the partial information of the address matches the partial information of the stored address.