Serial Interface Circuit with Programmable Control Register
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Solution Overview
Problem
Existing serial interface circuits require significant CPU involvement to handle various communication protocols, leading to increased load and inefficiency, especially when coping with different frame formats, as they need to write known data into FIFO registers synchronously and perform bit-by-bit comparisons.
Innovation Solution
A semiconductor device with a serial interface circuit that includes a rewritable control register to programmably specify the field structure of frames, allowing the circuit to analyze and process frames according to set parameters, reducing the need for CPU intervention by matching expected values before processing data fields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the serial interface circuit writes known data into FIFO register synchronously with receive action, then the frame format can be identified, but the CPU load increases and processing efficiency decreases
Solution Approach 1:
The patent pre-stores multiple types of frame format data (including preamble, control fields, and address fields) in the FIFO register before actual reception. This preliminary preparation allows the interface circuit to automatically compare and identify frame formats without requiring real-time CPU intervention during the reception process, thus reducing CPU load while maintaining accurate frame format identification.
Solution Approach 2:
The serial interface circuit performs self-service by automatically comparing received data with pre-stored frame format data and independently determining the frame structure. The interface circuit generates its own control signals (such as RxFIFOFull interrupt) without needing continuous CPU coordination, enabling autonomous frame format identification and reducing dependency on CPU processing.
2Measurement precision
If the interface circuit performs bit-by-bit comparison of receive data with known data, then the frame destination can be accurately judged, but the processing time increases
Solution Approach 1:
The patent pre-loads complete frame format patterns (including destination address information) into the FIFO register before reception begins. This allows the interface circuit to perform parallel comparison of entire frame structures rather than sequential bit-by-bit comparison, significantly reducing processing time while maintaining accurate destination judgment through comprehensive pattern matching.
Solution Approach 2:
The interface circuit continuously compares received data with pre-stored frame formats throughout the reception process without interruption. The comparison operation runs concurrently with data reception, eliminating idle time and ensuring continuous progress in frame identification. This continuous operation maintains high accuracy in destination judgment while minimizing overall processing time.
3Adaptability or versatility
If the CPU analyzes control and address fields of received frames, then various communication protocols can be handled, but the CPU load increases significantly
Solution Approach 1:
The serial interface circuit performs self-service by automatically analyzing control and address fields according to pre-stored frame format patterns. The interface circuit independently determines protocol types and destination addresses without requiring CPU execution of analysis software, thereby maintaining broad protocol compatibility while significantly reducing CPU processing requirements.
Solution Approach 2:
The FIFO register acts as an intermediary that stores both the received frame data and the corresponding expected frame format patterns. This intermediary structure enables the interface circuit to perform protocol analysis by comparing data with stored templates rather than requiring CPU to execute complex protocol handling logic, thus maintaining versatility while reducing CPU load.
4Extent of automation
If the interface circuit requests CPU interruption for every received frame, then frame processing can be triggered, but the CPU is overloaded with unnecessary processing requests
Solution Approach 1:
The interface circuit uses feedback from the comparison between received and expected frame data to automatically generate appropriate control signals. When the destination address matches the expected value, the circuit automatically sets the RxFIFOFull interrupt flag without requiring CPU intervention. This feedback mechanism enables automated frame processing while filtering out unnecessary CPU requests by pre-determining which frames require processing based on destination matching.
Data Source
AI summary
A serial interface circuit which can adapt to various frame formats to reduce the load on a CPU. The interface circuit includes a rewritable control register used for programmably specifying a field structure to be targeted for processing out of structures of fields preceding a data field of a frame as defined by a communication protocol. The interface circuit analyzes the field structure preceding the data field according to a setting of the control register. When a destination of a received frame is determined to match an expected value, the interface circuit issues a request for the CPU to process the data field information. After a setting is made on the control register, the serial interface circuit can adapt to various formats of frames as defined by a communication protocol according to the information held there, and can also analyze a destination.