Unified Serial Interface for Multi-Processor Debugging
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Solution Overview
Problem
Existing processor technologies face challenges in providing a unified, non-invasive interface for debugging and data acquisition across multiple processors within a single chip or networked chips, especially in complex systems where multiple processors communicate and debug interfaces are incomplete or bug-ridden, making it difficult to diagnose software and hardware issues without affecting the normal operation of the chips.
Innovation Solution
The development of a Serial Interface (SIF) system that includes both xSIF and iSIF interfaces, allowing for non-invasive access to processors' memory, registers, and debug instructions, enabling simultaneous monitoring and debugging of multiple processors with a single interface, and supporting both internal and external communication methods to maintain chip functionality and timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processors are integrated into a single chip, then processing capability and functionality are improved, but device complexity and difficulty of debugging increase
Solution Approach 1:
The patent segments the debugging function by providing separate debug interfaces for each processor while maintaining a unified architecture. Each processor has its own dedicated debug interface that can be independently accessed, allowing the debugging complexity to be distributed rather than concentrated in a single complex interface.
Solution Approach 2:
The patent creates a universal debug interface architecture that can access multiple processors through a standardized protocol. The same interface mechanism works for all processors in the chip, providing multi-functionality that reduces overall system complexity despite the increased number of processors.
2Difficulty of detecting and measuring
If debug interfaces are provided for each processor, then debugging capability is improved, but interface complexity and number of components increase
Solution Approach 1:
The patent merges multiple individual debug interfaces into a unified debug architecture. Instead of providing completely separate interfaces for each processor, the system combines them into a coordinated interface structure that shares common resources and control mechanisms, reducing overall interface complexity.
Solution Approach 2:
The patent introduces an intermediary debug controller or arbitration mechanism that mediates between multiple processor debug interfaces and the external debug tool. This intermediary layer manages access to different processors' debug interfaces, simplifying the external interface while maintaining comprehensive debugging capability.
3Reliability
If non-invasive access is provided to processor memory and registers, then reliability of normal operation is improved, but device complexity increases
Solution Approach 1:
The patent implements preliminary action by providing debug interfaces that are always available but remain inactive during normal processor operation. The debug interfaces are pre-configured and ready to access memory and registers without interfering with normal processing, activating only when needed for debugging purposes.
Solution Approach 2:
The patent extracts the debugging functionality into a separate, independent interface layer that operates independently from the main processor logic. By taking out debug access mechanisms from the core processor architecture and placing them in a separate interface layer, the system achieves non-invasive access without adding complexity to the main processing path.
4Ease of operation
If a unified interface supports multiple processors, then ease of operation and debugging is improved, but adaptability to different processor configurations decreases
Solution Approach 1:
The patent implements dynamics by making the unified debug interface adaptable through dynamic configuration. The interface can dynamically adjust its behavior based on which processors are present, their individual capabilities, and the current debugging requirements. This allows a single unified interface to handle different processor configurations without sacrificing ease of operation.
Data Source
AI summary
A data processing apparatus comprises a processor constructed to operate under control of a sequence of program instructions selected from a predetermined instruction set; master circuitry to request access to storage locations of the processor; an interface circuit to provide an interface for an external apparatus to signal a request for access to the storage locations and an interface for the master circuitry to signal a request for access to the storage locations; and control to provide access between the storage locations and the interface circuit in response to the request only at predetermined points in execution of the stored program, the control being operable to fix periods of time for providing such access relative to the sequence of program instructions such that execution timing of the stored instructions is independent of whether a request is supplied to the interface.