Serial Interface Diagnostic Coverage via Mode-Dependent CRC
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Solution Overview
Problem
Current serial interfaces, such as SPIs, have gaps in diagnostic coverage, failing to ensure that data is correctly read from a buffer and transmitted without errors, and cannot distinguish between user and test data modes, leading to potential errors and faulty decisions in safety-critical systems.
Innovation Solution
Implementing a serial interface with a data verification module that selects different error detection values based on mode signals, using a loopback circuit to verify data integrity, and clearing data buffers after transmission to prevent stale data, thereby enhancing diagnostic capabilities and fault detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional CRC and frame counter diagnostic techniques are used in SPI interfaces, then some transmission errors can be detected, but diagnostic coverage remains incomplete and cannot ensure data is current and error-free
Solution Approach 1:
The patent applies preliminary action by clearing the transmit buffer after successful transmission is detected. The read detector monitors the buffer read operation, and upon detecting that data has been read from the buffer, it activates the clear signal to clear the buffer. This preliminary clearing action prevents stale data from being transmitted in future operations, thereby improving diagnostic coverage without significantly increasing interface complexity.
2Reliability
If no buffer clearing mechanism is implemented, then the interface remains simple, but stale data may be transmitted causing errors in safety-critical systems
Solution Approach 1:
The patent implements self-service through the read detector, which automatically detects when data has been read from the transmit buffer and autonomously generates the clear signal to clear the buffer. This self-service mechanism ensures that stale data is prevented without requiring external intervention or complex buffer management logic, thereby improving data transmission accuracy while minimizing the increase in buffer management complexity.
3Reliability
If the transmit buffer is continuously monitored and cleared, then stale data transmission is prevented, but the system requires additional detection circuitry and control signals
Solution Approach 1:
The patent applies merging by integrating the read detector and clear signal generation into the existing SPI interface architecture. The read detector is combined with the buffer read operation, and the clear signal is merged into the existing buffer control logic. This consolidation approach enables stale data prevention while minimizing the increase in circuit complexity by reusing existing interface components rather than adding entirely separate monitoring and clearing systems.
Data Source
AI summary
A serial interface, such as a serial peripheral interface (SPI), with improved diagnostic coverage is disclosed. The serial interface includes a data verification module that selects an error detection value in response to a mode signal indicating if the transmitting device is in user mode or test mode. For example, the data verification module computes a cyclic redundancy check (CRC) value and selects either the computed CRC value or its inverse based on the mode. The receiving device can determine the mode of the transmitting device based on the error detection value used. The serial interface further includes a read detector for clearing the transmit data buffer after data is read out. The serial interface may further include a loopback circuit for verifying that the data output from an output pin matches the data from the transmit data buffer.