Serial Interface Timing Circuit for Fast Write-to-Read Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices with serial interfaces, consecutive read and write operations face issues where the read address may be acquired during write processing, leading to erroneous writing due to timing mismatches, necessitating an interval period that increases overall processing time.
Innovation Solution
A serial interface circuit and method that generate timing signals to hold and output bit groups in parallel form, allowing for simultaneous receipt of read addresses during write processing without waiting for write processing to end, enabling quick transition from write to read access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an interval period is provided to prevent address switching errors during write processing, then reliability is improved, but processing time increases
Solution Approach 1:
The read address is acquired and held in advance during the write processing period, so that when the write processing completes, the read address is already ready for immediate use. This preliminary acquisition of the read address eliminates the need for waiting time after write processing, thus reducing processing time while ensuring reliable address switching.
2Productivity
If the read access is started immediately after write access, then productivity is improved, but address switching errors occur
Solution Approach 1:
The read address is acquired and held in advance during the write processing period, so that when the write processing completes, the read address is already ready for immediate use. This allows immediate transition to read access without waiting, improving productivity while ensuring address accuracy through the holding mechanism.
Solution Approach 2:
A holding circuit acts as an intermediary to store the read address temporarily during write processing. This intermediary structure allows the read address to be prepared in advance and held ready, enabling immediate read access after write completion without address switching errors, thus improving both productivity and reliability.
3Loss of time
If the read address is acquired during write processing, then processing time is reduced, but address switching errors occur
Solution Approach 1:
The read address is acquired and held in advance during the write processing period, allowing immediate use after write completion. This preliminary action reduces transition time while the holding mechanism ensures address accuracy by preventing unintended switching.
Solution Approach 2:
A holding circuit serves as an intermediary to temporarily store the read address during write processing. This intermediary structure enables the read address to be prepared in advance and held ready, allowing immediate read access after write completion without address switching errors, thus reducing transition time while maintaining reliability.
Data Source
AI summary
A serial interface circuit, a semiconductor device, and a serial-parallel conversion method are provided. The disclosure is to generate first to nth timing signals respectively indicating timings that differ by 1 bit cycle of the bit string when receiving a serial signal including the bit string in a serial form and converting the bit string into a parallel form to obtain a parallel bit group. Each bit in the bit string is held at the timings of the first to tth timing signals as the standby bit group, the standby bit group is acquired at the timing of any one of the (t+1)th to nth timing signals as a part of the parallel bit group, and each bit in the bit string is held at the timings of the (t+1)th to nth timing signals and the held bit group is set as another part of the parallel bit group.