Serial Interface Clock Recovery Without Wake-Up Handshake Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In UHS-II/-III memory card interface standards, the time required for the inner clock to stabilize after a state change, such as from dormant to active, is lengthy due to the low frequency reference clock, leading to increased latency and power consumption in low power modes where the PLL circuit remains operational.
Innovation Solution
An interface system that stops the supply of the reference clock during the dormant state and omits the handshake check upon returning to the active state, utilizing a controller to manage the clock generators and sampling circuit to rapidly recover and reduce standby power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the reference clock is supplied continuously to maintain PLL operation in low power modes, then the clock stability is improved, but the power consumption increases
Solution Approach 1:
The reference clock is supplied periodically rather than continuously. The clock supply is activated only when needed for PLL operation and suspended during dormant periods, transforming continuous clock supply into periodic action to reduce power consumption while maintaining stability when required
Solution Approach 2:
The system performs preliminary actions by storing synchronization information and clock state data before entering dormant mode. This allows the PLL to rapidly resume operation without requiring continuous clock supply, as the preliminary stored information enables quick recovery
2Reliability
If the handshake check is performed upon returning from dormant state, then the synchronization reliability is improved, but the latency increases
Solution Approach 1:
The synchronization check information is prepared and stored in advance before the dormant period ends. This preliminary preparation allows the system to resume data transfer immediately without performing a full handshake check, thereby reducing latency while maintaining synchronization reliability through the pre-computed information
Solution Approach 2:
Instead of performing a complete handshake check upon recovery, the system uses a simplified verification based on copied/stored synchronization state information. This copy-based approach maintains reliability by verifying against pre-stored valid state data while avoiding the time-consuming full handshake procedure
3Stability of the object's composition
If the PLL circuit remains operational in low power modes, then the clock stability is improved, but the power consumption increases
Solution Approach 1:
The PLL circuit operates dynamically, switching between operational and suspended states based on the device's activity level. During active modes, the PLL is operational providing stable clocks; during dormant modes, the PLL is suspended to eliminate standby power consumption, with rapid resume capability when needed
Solution Approach 2:
The system discards continuous PLL operation during dormant periods to eliminate unnecessary power consumption. The PLL functionality is recovered quickly when needed by utilizing pre-stored synchronization information, allowing the system to discard and recover the clock generation function as needed without maintaining continuous operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces standby power and enables rapid recovery from a dormant state to an active state, minimizing latency and power consumption by allowing immediate data transfer without the need for a handshake check, while maintaining efficient data synchronization.
Implementation Method 1
The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock
Data Source
AI summary
According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.