Serial Multiplex Inverter Current Detection Delay Reduction
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Solution Overview
Problem
Current methods for detecting output current in serial multilevel inverters suffer from significant current detection delay, which hampers high-response current control, especially when dealing with inductive loads like motors, due to the inherent delay in moving average operations synchronized with carrier cycles.
Innovation Solution
The method involves setting the moving average width to match the PWM control cycle and synchronizing it with the carrier signal peak, while also shortening the sampling interval to half of the moving average width, thereby minimizing current detection delay without compromising accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the moving average width is set to the carrier cycle for accurate current detection, then the current detection accuracy is improved, but the current detection delay increases
Solution Approach 1:
The patent divides the moving average operation into multiple stages corresponding to different carrier cycles. By segmenting the calculation process and utilizing the phase differences between multiple carrier signals, the system performs moving average operations on individual carrier cycles rather than waiting for a complete carrier cycle to finish, thereby reducing detection delay while maintaining accuracy.
Solution Approach 2:
The patent performs preliminary moving average calculations on previous carrier cycles and stores these results. When current detection is needed, the system uses these pre-calculated values along with partial current data to quickly determine the current detection value, eliminating the need to wait for the full carrier cycle to complete before starting the moving average operation.
2Speed
If the sampling interval is reduced to decrease detection delay, then the response speed is improved, but the computational complexity increases
Solution Approach 1:
The patent employs periodic sampling at specific intervals synchronized with the carrier signal phases. Instead of continuous sampling, the system samples at predetermined points within each carrier cycle, maintaining adequate detection speed while significantly reducing the computational burden compared to continuous or overly frequent sampling.
Solution Approach 2:
The patent dynamically adjusts the sampling interval based on the carrier cycle phase and the specific detection requirements. By changing the sampling parameters adaptively rather than using a fixed high-frequency sampling rate, the system achieves fast response where needed while reducing computational complexity in other phases.
Data Source
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AI summary
[Object] To detect an output current with a current detection delay shortened without decreasing accuracy of current detection. [Means to solve] In a serial multilevel inverter, in which each phase of a three-phase inverter is configured by connecting outputs of n-stage single-phase inverters in series, a current control (ACR) is performed by a detection current obtained by calculating a moving average of a sampling value of each phase output current of the three-phase inverter, and 2n carrier signals are shifted to a [360/2n] phase difference and are compared with a voltage command for a PWM control of the each single-phase inverter, a moving average width Tc is set to the same time as a PWM control cycle (1/2n of a cycle Tcarry of a carrier signal) and is synchronized with a peak of the carrier signal, and a sampling interval Tsmp is set to 1/2 of the moving average width Tc or less and is synchronized with the carrier signal. The current control cycle is set to the sampling interval Tsmp.