Differential Serial I/O with Forwarded Clock for Low-Latency Links
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Solution Overview
Problem
Conventional high-speed I/O data circuits face inefficiencies in data transfer due to high memory requirements, latency penalties, and suboptimal digital design methods, leading to a trade-off between faster intra-chip communication and higher manufacturing costs versus slower inter-chip communication with lower costs.
Innovation Solution
A high-speed I/O data system utilizing differential serializing transmitters with multi-phase clock generators and pulse-controlled push-pull output drivers, which reduces power consumption and silicon area while maintaining high-speed data transfer, implemented with CMOS logic for improved speed-power ratio and reduced latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional I/O interfaces are used, then design flexibility is maintained, but data transfer speed is insufficient for high-speed applications
Solution Approach 1:
The patent changes the fundamental parameters of the I/O interface by transitioning from parallel to serial communication architecture, implementing differential signaling, and using pulse-based data encoding instead of conventional voltage levels. These parameter changes enable data transfer speeds exceeding 10 Gb/s while maintaining design flexibility through configurable serialization ratios and adjustable clock frequencies.
2Productivity
If packet-based communication is implemented, then data transfer capability is improved, but memory requirements and latency increase
Solution Approach 1:
The patent extracts the packetization and buffering functions from the I/O interface itself, implementing instead a continuous stream-based serial communication protocol. By removing the need for packet assembly and memory buffering at the interface level, the design achieves lower latency while maintaining high data transfer capability through efficient clock-synchronized data transmission.
3Speed
If full-custom I/O solutions are attempted, then performance may be improved, but power supply noise and signal integrity issues arise
Solution Approach 1:
The patent converts potential harmful effects into beneficial ones by using differential signaling to cancel out power supply noise and electromagnetic interference, and by employing pulse-based encoding that is inherently more robust to signal degradation. The serialized architecture reduces the bandwidth requirement per signal line, improving signal integrity while maintaining high data rates.
4Device complexity
If data is transmitted in parallel form, then simplicity is maintained, but signal integrity control and power consumption become problematic at high speeds
Solution Approach 1:
The patent segments the parallel data bus into multiple serial channels, transmitting data bit-by-bit over time rather than all bits simultaneously. This segmentation reduces the instantaneous power consumption per channel and improves signal integrity by lowering the bandwidth requirement for each individual signal line, while the overall data throughput is maintained through multiplexing.
Data Source
AI summary
In embodiments of a high-speed I/O data system, a first computer chip includes a data transmission system, and a second computer chip includes a data reception system. A data channel communicates an NRZ data signal, and a clock channel communicates a forwarded clock signal, from the data transmission system to the data reception system. The data transmission system includes a first differential serializing transmitter to generate the NRZ data signal from pulsed data, and further includes a second differential serializing transmitter to generate a forwarded clock signal. A first multi-phase transmit clock generator generates transmit clock signals for the first and second differential serializing transmitters. The data reception system includes a data receiver and a de-serializer to receive and de-serialize the NRZ data signal, and includes a multi-phase receive clock generator to generate receive clock signals from the forwarded clock signal for the de-serializing data receiver.