Serial Link Clock Generator Using Fractional-N Jitter Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed serial data links, such as SATA, require precision clocks at both ends, but using crystal oscillators increases cost; existing solutions that recover the clock from the data signal lead to complex and power-hungry designs due to stringent jitter requirements.
Innovation Solution
A transceiver with a clock generator comprising a local clock, frequency difference detector, and fractional-N frequency synthesizer, which recovers a reference clock from the data signal and synthesizes a transmit clock with reduced jitter, using a ceramic resonator instead of a crystal oscillator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a crystal oscillator is used at each end of the data link to generate precision local clock signals, then the required precision clock signal is achieved, but the cost increases
Solution Approach 1:
The patent replaces expensive crystal oscillators with cheaper ceramic resonators for generating local clock signals. The ceramic resonator, while less precise than a crystal oscillator, provides sufficient precision when combined with the fractional-N frequency synthesizer that corrects frequency deviations, achieving cost reduction while maintaining adequate clock precision for the application
Solution Approach 2:
The patent introduces a fractional-N frequency synthesizer as an intermediary component between the ceramic resonator and the transmit clock. This synthesizer acts as a frequency correction mechanism that compensates for the lower precision of the ceramic resonator, enabling the use of cheaper resonators while maintaining the required clock signal precision through digital frequency synthesis and phase adjustment
2Ease of manufacture
If the transmit clock is generated by recovering the receive clock from the received data signal, then the device can use a cheaper ceramic resonator, but the design becomes more complex and power-hungry due to stringent jitter requirements
Solution Approach 1:
The patent replaces the traditional analog clock data recovery (CDR) circuit with a digital fractional-N frequency synthesizer. This substitution of digital logic for analog circuitry reduces design complexity and power consumption while meeting the stringent jitter requirements. The digital synthesizer uses phase-frequency detectors and digital phase accumulators to achieve precise frequency and phase control without the complexity of high-performance analog CDR circuits
Solution Approach 2:
The patent employs a dynamic fractional-N frequency synthesizer that continuously adjusts the transmit clock frequency and phase based on comparisons with the recovered receive clock. The system dynamically corrects frequency deviations and phase errors through digital control mechanisms, enabling flexible adaptation to clock variations while maintaining low jitter performance without requiring complex fixed analog circuitry
3Ease of manufacture
If the transmit clock is generated by recovering the receive clock from the received data signal, then the device can use a cheaper ceramic resonator, but power consumption increases
Solution Approach 1:
The patent replaces power-hungry analog clock data recovery circuits with a more power-efficient digital fractional-N frequency synthesizer. The digital implementation uses standard CMOS logic circuits including phase-frequency detectors and digital phase accumulators that consume significantly less power than the high-performance analog CDR circuits required to meet jitter specifications, thereby reducing overall device power consumption while enabling the use of ceramic resonators
Data Source
AI summary
A clock generator is provided for a transmitter in a transceiver adapted to communicate data over a serial data link. The transceiver includes a clock data recovery circuit recovers a receive clock signal and outputs a reference clock signal. The clock generator includes a local clock, a frequency difference detector, and a fractional-N frequency synthesizer. The local clock outputs a local clock signal. The frequency difference detector outputs a fractional frequency difference signal based on a frequency difference between the local clock signal and the reference clock signal. The fractional-N frequency synthesizer outputs a transmit clock signal having a same frequency as the recovered receive clock signal.