Full-Duplex Serial Link Clock Synchronization
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Solution Overview
Problem
Full-duplex synchronous serial links in automotive applications face delays due to galvanic isolation and wire length, which disrupt data synchronization with clock signals, limiting communication speeds to below 5 Mbits/s.
Innovation Solution
A method that synchronizes data and clock signals by applying a consistent delay across all wires, allowing the clock signal to be sent back to the first system, ensuring that both systems receive messages in phase with the clock, even across galvanic isolation, thereby enabling high-speed communication above 5 Mbits/s.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If galvanic isolation is installed to protect ELV components from LV, then data synchronization is disrupted and communication speed is limited to below 5 Mbits/s
Solution Approach 1:
The patent applies preliminary action by sending the clock signal through the galvanic isolation barrier in advance, before data transmission. This allows the receiving system to pre-synchronize its sampling clock with the transmitted clock signal, compensating for the delay introduced by galvanic isolation. The method proactively addresses the synchronization issue by establishing timing reference beforehand, enabling high-speed communication while maintaining protection.
2Ease of operation
If wire length is increased to connect systems, then communication delay increases and phase synchronization is lost
Solution Approach 1:
The patent implements feedback by transmitting the clock signal through the same communication channel (including the full wire length and galvanic isolation) that carries data. The receiving system uses this feedback clock signal to synchronize its sampling operations, automatically compensating for any delay introduced by wire length. This feedback mechanism ensures that phase synchronization is maintained regardless of the physical distance between systems.
3Speed
If communication speed is increased above 5 Mbits/s, then delay-induced phase issues prevent correct data sampling
Solution Approach 1:
The patent applies equipotentiality by ensuring that both data and clock signal experience the same transmission conditions and delays through galvanic isolation and wire routing. By subjecting both signals to identical transmission paths and delays, the relative phase relationship between clock and data is preserved, allowing correct sampling at high speeds. This equal treatment of signals eliminates the phase synchronization problems that would otherwise occur.
Data Source
AI summary
A method for communicating between a first system and a second system using a full-duplex synchronous serial link capable of simultaneously routing between both systems is disclosed. The data involved includes at least one message from the first system to the second, at least one message from the second system to the first, and a clock signal. The method involves the second system receiving a message and a clock signal sent by the first system, delayed and substantially in phase, the second system sends a message to the first system, the clock signal received by the second system is sent back to the first system with the message sent by the second system, and the first system receives the message sent by the second system and the sent-back clock signal, delayed and substantially in phase.