Adaptive Serial Link Clocking with Delay-Chain Edge Generation
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Solution Overview
Problem
Conventional high-speed serial link clocking mechanisms incur latency, area, and energy consumption due to the use of two asynchronous FIFOs, and are affected by voltage noise, which does not adapt to supply voltage changes.
Innovation Solution
Adaptive clock generation using a delay-chain-based edge generation circuit that operates synchronously with the transmitter clock, generating additional edges for data transmission and adapting to voltage noise, thereby reducing the need for asynchronous FIFOs and improving energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a fixed-frequency clock (clk2) is used to provide additional digital signal edges for high-speed serial link, then data transfer rate is increased, but voltage noise reduces link margin because the clock does not adapt when supply voltage changes
Solution Approach 1:
The patent applies dynamics by making the clock frequency adaptive rather than fixed. The clocking circuit dynamically adjusts its operating frequency in response to supply voltage changes, allowing it to maintain reliable operation across varying voltage conditions while still providing the high-speed edges needed for increased data transfer rates.
Solution Approach 2:
The patent changes the parameter of clock frequency from a fixed value to a variable that adapts to supply voltage conditions. By monitoring supply voltage and adjusting the clock frequency accordingly, the system maintains optimal link margin while achieving high data transfer rates, resolving the contradiction between speed and reliability.
2Ease of operation
If two asynchronous FIFOs are used to communicate data between different clock domains, then data transfer between clock domains is enabled, but latency is added to the link and area and energy consumption increase
Solution Approach 1:
The patent merges the clock domains by using a single shared clocking circuit for both the high-speed serial link and the digital logic. This eliminates the need for asynchronous FIFOs to bridge clock domains, thereby reducing latency and area while maintaining ease of operation for data communication.
Solution Approach 2:
The patent extracts and eliminates the asynchronous FIFO structures from the system by synchronizing the clock domains. By removing these intermediate buffering components, the system achieves lower latency and reduced area consumption while still enabling data communication between what would have been different clock domains.
3Productivity
If a higher frequency clock (e.g., 16 GHz) is used for the serial link compared to digital logic (e.g., 2 GHz), then data transfer rate is increased, but area and energy consumption increase
Solution Approach 1:
The patent applies dynamics by making the high-frequency clock adaptive to supply voltage conditions. The clocking circuit dynamically adjusts its frequency based on available power, allowing the system to achieve high data transfer rates when voltage is stable while reducing frequency and energy consumption when voltage fluctuates, thus resolving the contradiction between productivity and energy use.
Data Source
AI summary
Adaptive clock mechanisms for serial links utilizing a delay-chain-based edge generation circuit to generate a clock that is a faster (higher-frequency) version of an incoming digital clock. The base frequency of the link clock utilized by the line transmitters is determined by the (slower) clock utilized by the digital circuitry supplying data to the line transmitters. An edge generator that may be composed of only non-synchronous circuit elements multiplies the edges of the slower clock to generate the link clock and also a clock forwarded to the receiver at a phase offset from the link clock.