Multiple Serial Link Memory for Flash Throughput
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Solution Overview
Problem
Current Flash memory technology is inadequate for high data rate applications due to limitations in programming and read throughput, primarily caused by signal quality issues at high operating frequencies, which result in increased latency and reduced capacity, especially in mobile electronic devices.
Innovation Solution
The implementation of semiconductor memory devices with multiple memory banks and multiple serial data link interfaces, where control circuitry independently controls data transfer between link interfaces and memory banks, enabling concurrent operations and reducing the number of pins required, thereby enhancing throughput and capacity while maintaining signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operating frequency of Flash memory is increased to improve data transmission speed, then programming and read throughput are improved, but signal quality deteriorates due to cross-talk, signal skew, and signal attenuation
Solution Approach 1:
The patent divides the memory system into multiple independent memory banks (Bank 0, Bank 1, etc.) that can be accessed concurrently through different serial data link interfaces. This segmentation allows the system to achieve high throughput by parallelizing access to multiple banks without requiring a single high-speed parallel interface, thus avoiding signal quality issues while maintaining fast data transmission.
2Productivity
If a parallel interface with multiple pins is used to increase data throughput, then data transmission capacity is improved, but the number of pins and wires increases causing inter-symbol interference, signal skew, and cross-talk
Solution Approach 1:
The patent replaces the mechanical/electrical parallel interface system with multiple pins and wires with a serial data link interface system. By using serial communication protocols and multiple independent serial links, the system achieves high data throughput without requiring a large number of physical pins, thereby eliminating inter-symbol interference, signal skew, and cross-talk associated with parallel interfaces.
3Productivity
If multiple parallel data buses are used to increase memory capacity and speed, then data transmission rate is improved, but routing congestion and chip size increase
Solution Approach 1:
The patent segments the memory system into multiple independent banks that can be accessed through separate serial data links. This approach achieves high data transmission rates by enabling concurrent access to multiple banks without requiring extensive parallel routing infrastructure, thereby reducing routing congestion and minimizing chip area while maintaining high productivity.
Data Source
Figure 1A~1B
Figure 1C
Figure 2A
AI summary
An apparatus, system, and method for controlling data transfer between a serial data link interface and memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple serial data links and multiple memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.