Serial Link Signal Conditioning for Phase Noise Jitter Attenuation
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Solution Overview
Problem
Existing serial data communications technologies face challenges in effectively addressing phase noise jitter in serial data communications links, as linear equalizers are transparent to phase noise jitter and require non-linear CDR loops, which complicates link training and conditioning.
Innovation Solution
A delay-locked tuning loop is employed to provide time domain delay modulation, using a tunable delay element and phase comparator circuitry to generate conditioned data signals independent of voltage domain frequency response, effectively attenuating phase noise jitter without requiring retiming or protocol awareness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If linear equalizers are used to correct for intersymbol interference, then ISI correction is achieved, but the system becomes transparent to phase noise jitter and cannot attenuate it
Solution Approach 1:
The system segments the signal conditioning function into two independent parts: a linear equalizer for ISI correction and a separate delay-locked loop for phase noise jitter attenuation. This allows each component to specialize in its respective function without compromising the other.
Solution Approach 2:
A delay-locked loop acts as an intermediary component between the linear equalizer output and the final output. It receives the equalized signal and applies additional phase noise jitter attenuation through delay modulation, serving as a mediator that adds the missing jitter attenuation function.
2Object-affected harmful factors
If CDR loops are used to reject input phase noise jitter, then phase noise rejection is achieved, but the system becomes inherently non-linear and complicates link training
Solution Approach 1:
The patent replaces the traditional CDR loop mechanism with a delay-locked loop that uses delay modulation instead of phase detection and feedback. This substitution maintains phase noise jitter rejection while preserving linearity and simplifying link training procedures.
Solution Approach 2:
The system changes the operating parameter from phase domain (used in CDR loops) to delay domain. By controlling delay instead of phase, the system achieves phase noise jitter rejection while maintaining linearity, as delay modulation does not introduce the non-linearities inherent in phase-locked operations.
3Object-affected harmful factors
If delay-locked tuning loop with time domain delay modulation is used, then phase noise jitter attenuation is achieved with linear transmission, but additional circuitry is required
Solution Approach 1:
The delay-locked loop is designed to perform multiple functions: it provides phase noise jitter attenuation, maintains signal timing alignment, and works seamlessly with the existing linear equalizer. This multi-functionality justifies the added circuitry by delivering multiple benefits from a single component.
Solution Approach 2:
The delay-locked loop incorporates feedback mechanisms that monitor the phase relationship between the input and output signals and automatically adjust the delay to optimize phase noise jitter attenuation. This feedback control enables the system to adapt to varying signal conditions without manual intervention.
Data Source
AI summary
A signal conditioner for use in a serial data communications link. The signal conditioner including a tunable delay element responsive to a tuning signal to provide time domain delay modulation of the input data signals to generate conditioned (output) data signals, and phase comparator circuitry to generate the delay tuning signal based on a detected phase error between feedback conditioned data signals, and a reference signal. The tunable delay element and the phase comparator circuitry forming a delay-locked tuning loop to phase lock the conditioned data signals to the reference signal, independent of voltage domain frequency response. An example signal conditioner is a jitter attenuator/cleaner, where the bandwidth of the reference signal is lower than the bandwidth of the delay-locked tuning loop, to provide a low-jitter reference signal.