Built-in Test for High-Speed Serial Link Margin Characterization
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Solution Overview
Problem
Determining the operating margin of high-speed differential links in processor-based communication systems is challenging due to device aging, temperature, and noise, making it difficult to establish a low bit error rate without prolonged testing.
Innovation Solution
A method involving integrated circuits with programmable phase generators and transmit drivers to dynamically shift clock signals and differential voltages, determining the failure points to establish time and voltage margins for reliable data sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If prolonged testing is used to determine bit error rate, then reliability measurement accuracy is improved, but testing time and productivity are worsened
Solution Approach 1:
The patent applies preliminary action by performing stress testing during the manufacturing process itself, specifically during silicon characterization. The built-in test feature enables premature determination of link margins and failure points before the device is deployed, allowing reliability to be established without requiring prolonged post-manufacturing testing. This shifts the testing activity to an earlier stage in the product lifecycle.
Solution Approach 2:
The patent implements self-service through the built-in test feature that enables the device to test its own link reliability and determine failure points autonomously. The test feature includes a phase generator that can programmably shift clock signals and a failure detection mechanism that automatically identifies when the link fails, eliminating the need for external testing equipment and prolonged manual testing procedures.
2Measurement precision
If external testing equipment is used to measure link margins, then measurement capability is improved, but device complexity and ease of operation are worsened
Solution Approach 1:
The patent implements self-service by embedding the complete testing capability within the device itself. The built-in test feature includes a phase generator that can programmably shift clock signals, a failure detection mechanism that automatically identifies when the link fails, and the ability to determine link margins autonomously. This eliminates the need for complex external testing equipment and specialized test setups.
Solution Approach 2:
The patent applies universality by designing the built-in test feature to perform multiple functions: it can determine link margins, identify failure points, measure time margin, and characterize device performance under various conditions. This multi-functional test feature replaces what would traditionally require multiple separate external testing instruments and procedures.
3Reliability
If stress testing is performed to determine failure points, then reliability characterization is improved, but manufacturing time and productivity are worsened
Solution Approach 1:
The patent applies preliminary action by performing reliability characterization during the manufacturing process itself rather than after. The built-in test feature enables premature determination of link margins and failure points during silicon characterization, allowing multiple devices to be tested in parallel without requiring prolonged post-manufacturing validation, thereby improving throughput.
Solution Approach 2:
The patent implements self-service by enabling each silicon device to test its own reliability characteristics autonomously during manufacturing. The test feature includes a phase generator that can programmably shift clock signals and a failure detection mechanism that automatically identifies failure points, eliminating the need for manual intervention and prolonged testing cycles, thus accelerating the characterization process.
Data Source
AI summary
A method of ensuring robust operation of a differential serial link is provided. The method provides a first integrated circuit having 1) a phase generator constructed and arranged to provide a programmable shift of a clock signal based on selective interpolating between first and second phases of the clock signal relative to a digital phase value, and 2) a transmit driver constructed and arranged to control, in a programmable manner, a differential voltage of digital data signals. A second integrated circuit is constructed and arranged to receive the clock and digital data signals sent by the first integrated circuit. The clock and digital data signals are sent substantially simultaneously through the link from the first integrated circuit to the second integrated circuit. It is determined whether the digital data signals can be sampled reliably by the second integrated circuit relative to the digital phase value. The clock signal is shifted, based on changing the digital phase value supplied to phase generator, towards a transition of the data signals until a failure is detected relative to an identified phase value such that the digital data signals cannot be sampled reliably by the second integrated circuit. Based on detection of the failure relative to the corresponding identified phase value, a time margin of the clock signal is established wherein the digital data signals can be sampled reliably by the second integrated circuit. A voltage margin of the differential voltage is also provided.