Serial Link Interface for High-Speed Scan Testing
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Solution Overview
Problem
Existing integrated circuit scan architectures require additional overhead circuitry for testing, which is not capable of supporting high-speed scan tests and increases test time due to the need for independent pins for each scan chain.
Innovation Solution
Incorporating a serial link interface that functions during both normal and test modes, allowing data transfer between the serial link interface and scan chains without going through the scan chain during normal operation, and using high-speed serial interfaces like PCI-Express for efficient scan testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional scan architectures with multiple scan chains are used, then test coverage is improved, but the number of external pins required increases
Solution Approach 1:
The patent applies multi-functionality by making the serial link interface serve dual purposes: it functions as both a normal operational communication interface and a scan test interface. This eliminates the need for separate dedicated scan pins, allowing the same physical interface to be used for both data communication and scan testing, thereby reducing the number of external pins required while maintaining comprehensive test coverage through multiple scan chains
2Reliability
If additional test circuitry is added for multiple scan chains, then test capability is improved, but device complexity and overhead increase
Solution Approach 1:
The patent makes the serial link interface universal by enabling it to perform both normal data communication and scan testing functions. The interface includes multiplexing circuitry that can route data flow appropriately based on operational mode, eliminating the need for separate dedicated test circuitry and reducing overall device complexity while maintaining full test capability
Solution Approach 2:
The patent merges the normal operational interface and scan test interface into a single unified serial link interface. By combining these two previously separate functions into one interface structure, the patent reduces circuitry overhead and eliminates the need for additional dedicated test hardware, thereby reducing device complexity while preserving comprehensive testing capability
3Adaptability or versatility
If conventional interfaces are used for scan testing, then compatibility is maintained, but test speed is limited
Solution Approach 1:
The patent changes the operational parameters of the serial link interface by utilizing high-speed serial communication capabilities (such as PCI-Express speeds) for scan testing. This allows the interface to operate at much higher data rates during test mode compared to conventional scan interfaces, thereby increasing scan test speed while maintaining compatibility with existing high-speed serial bus standards
4Ease of operation
If independent scan in and out pins are used for each scan chain, then scan testing is simplified, but test time increases
Solution Approach 1:
The patent merges the scan in and scan out operations into a single serial link interface that handles both functions. By combining these operations and utilizing high-speed serial communication, the patent reduces the time required for data transfer while maintaining the simplicity of the scanning process, thereby reducing overall test time without complicating the operation
Data Source
AI summary
In one embodiment, an integrated circuit includes a serial link interface configured to send and receive data over a serial bus both during normal operation and during scan tests. The integrated circuit may include data routing circuitry for transferring data between the serial link interface and a scan chain during a scan test, and for transferring data between the serial link interface and a core logic circuit of the integrated circuit, without going through the scan chain, during normal operation. Scan data may be generated and analyzed by a tester integrated circuit coupled to the integrated circuit over the serial bus.