Serial Data Lock Retry in Imaging Receiver Synchronization
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Solution Overview
Problem
Imaging apparatuses face challenges in reliably transmitting high-speed image data from CMOS image sensors due to the complexity of clock data recovery and skew adjustment in differential signal transmission, particularly with increased pixel density leading to signal transmission bottlenecks.
Innovation Solution
The imaging apparatus incorporates a data reception unit with a clock data recovery circuit and skew adjustment mechanism, utilizing a frequency locked loop and phase locked loop to synchronize clock signals with embedded clock procedures, ensuring reliable data transmission and reducing power consumption by retraining circuits during image capture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-speed serial data transmission is implemented to increase output rate, then productivity is improved, but reliability deteriorates due to clock data recovery complexity and skew adjustment difficulties
Solution Approach 1:
The patent implements a feedback mechanism where the reception unit detects lock state information from the clock data recovery circuit and reports it to the control unit. When locking fails, the control unit automatically retries the locking operation, creating a closed-loop feedback system that ensures reliable data transmission while maintaining high-speed operation.
Solution Approach 2:
The patent performs preliminary clock data recovery and locking operations before actual image data transmission begins. The control unit initiates locking operations in advance, detects lock state, and ensures synchronization is established before high-speed data transfer starts, preventing transmission errors.
2Reliability
If clock data recovery and skew adjustment circuits are continuously active to maintain synchronization, then reliability is improved, but use of energy worsens
Solution Approach 1:
The patent employs periodic locking operations instead of continuous operation. The control unit determines whether to perform locking operations based on whether image data is being transmitted, and the reception unit only actively performs clock data recovery when needed. This periodic activation maintains synchronization reliability while significantly reducing power consumption during idle periods.
Solution Approach 2:
The reception unit autonomously detects lock state information and reports it to the control unit without requiring continuous external control signals. The system uses its own operational state information to trigger appropriate actions, reducing the need for continuous power-consuming control operations.
3Reliability
If locking operation is performed multiple times to ensure data reception, then reliability is improved, but loss of time increases due to repeated locking attempts
Solution Approach 1:
The feedback mechanism allows the system to quickly detect locking success or failure and immediately retry if needed. The control unit receives lock state information and makes rapid decisions about whether to perform additional locking operations, minimizing unnecessary time delays while ensuring reliable data reception when locking fails initially.
Solution Approach 2:
The patent implements a retry mechanism that performs locking operations multiple times only when necessary. Instead of always performing extensive locking sequences, the system uses a partial approach: it attempts locking once, and only performs additional locking operations if the first attempt fails, as determined by the lock state detection. This reduces average time loss while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient and reliable high-speed image data transmission, maintaining power efficiency by minimizing the duration of active circuits during data transfer, thus addressing signal transmission bottlenecks and improving image capture reliability.
Implementation Method 1
utilizing a frequency locked loop and phase locked loop to synchronize clock signals with embedded clock procedures
Implementation Method 2
utilizing a frequency locked loop and phase locked loop to synchronize clock signals with embedded clock procedures
Data Source
AI summary
An imaging apparatus allows a clock data recovery device to reestablish reception of data even when the clock data recovery device has failed to lock a phase. A reception unit includes a locking unit configured to perform a locking operation for receiving the data and a detection unit configured to detect a lock state of the locking unit. A control unit controls performing of the locking operation again by the locking unit in a case where a lock is not achieved, based on a detection result detected by the detection unit.