Serial Memory Interface Partitioning for Low-Latency Acknowledgements
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Solution Overview
Problem
Programmable integrated circuits face challenges in supporting multiple serial memory interface protocols and minimizing acknowledgement processing latency, particularly due to limited retransmission buffer sizes, which can reduce link performance.
Innovation Solution
A programmable integrated circuit with a memory interface that combines programmable logic and hardwired logic, featuring a soft memory controller for packet formation, a cyclic redundancy check checking circuit, and a retransmission buffer to manage sequence numbers and acknowledgements, ensuring compatibility with various protocols and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a programmable integrated circuit uses a soft memory controller with packet formation logic to support multiple serial memory interface protocols, then adaptability to different memory types is improved, but acknowledgement processing latency increases due to the programmable logic processing overhead
Solution Approach 1:
The memory interface is segmented into two distinct parts: a soft memory controller in programmable logic for protocol adaptability and a hardwired logic circuit for time-critical packet processing functions. This segmentation allows each part to be optimized for its specific function, resolving the contradiction between adaptability and latency.
Solution Approach 2:
A hardwired logic circuit acts as an intermediary between the soft memory controller and the external memory interface. This intermediary handles time-critical packet processing functions (CRC checking, sequence number extraction, acknowledgment substitution) in parallel with the programmable logic, thereby reducing overall processing latency while maintaining protocol flexibility.
2Device complexity
If the retransmission buffer size is kept small to save resources, then device complexity and resource usage are reduced, but link performance deteriorates in the presence of acknowledgement processing latency
Solution Approach 1:
The hardwired logic circuit implements rapid feedback mechanisms by quickly processing acknowledgments and substituting them into outgoing packets. This fast feedback loop allows the system to maintain high link performance even with small retransmission buffers, as packets can be rapidly retransmitted when needed without being bottlenecked by slow acknowledgment processing.
3Speed
If hardwired logic circuitry is added to reduce acknowledgement processing latency, then processing speed is improved, but device complexity increases
Solution Approach 1:
Hardwired logic is applied locally only to the specific functions that require high-speed processing (CRC checking, sequence number extraction, acknowledgment substitution), while the rest of the memory controller remains in programmable logic. This localized application of hardwired logic minimizes the increase in overall device complexity while achieving the speed improvement where it is most needed.
Data Source
AI summary
A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet formation logic that creates packets that include empty fields for sequence number information, acknowledgement information, and cyclic redundancy check information. The hardwired circuitry of the memory interface may be used to insert a sequence number, an acknowledgement, and cyclic redundancy check information into the empty fields.