Variable Latency Serial Memory Bus Signaling
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Solution Overview
Problem
Existing serial memory devices require a dedicated signal line to implement variable read latency, which increases the size, pin count, and interconnect cost, necessitating a solution that eliminates the need for this dedicated line.
Innovation Solution
A method and system that implement variable read latency on a serial input/output memory data interface by communicating commands, forcing data lines to a logic state, detecting a limited duration signal, and reading data after the signal's end, without using additional dedicated signal lines, thereby adapting read latency to memory latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a dedicated signal line is added to implement variable read latency, then memory access efficiency is improved, but pin count and device complexity increase
Solution Approach 1:
The patent combines the latency signaling function with the existing data I/O lines by using bidirectional communication. The memory device asserts a ready signal on the same data lines used for data transfer, eliminating the need for dedicated latency signal lines. This merging of functions resolves the contradiction by maintaining improved memory access efficiency while avoiding increased pin count.
Solution Approach 2:
The data I/O lines are made multi-functional by serving both data transfer purposes and latency signaling purposes. The memory device uses these universal lines to assert ready signals during read operations, allowing the same physical infrastructure to support both data communication and latency management without requiring additional dedicated lines.
2Productivity
If a dedicated signal line is added to implement variable read latency, then memory access efficiency is improved, but interconnect cost increases
Solution Approach 1:
The patent merges the latency signaling function into the existing data I/O interconnect structure. By using the same physical lines for both data transfer and ready signal assertion, the invention eliminates the need for separate interconnects, thereby maintaining improved memory access efficiency while reducing interconnect cost and manufacturing complexity.
Solution Approach 2:
The existing data I/O infrastructure serves dual purposes by automatically handling both data transfer and latency signaling functions. The memory device leverages the already-present interconnect structure to provide ready signals, making the system self-sufficient and eliminating the need for additional dedicated interconnects that would increase manufacturing cost.
3Adaptability or versatility
If a dedicated signal line is added to implement variable read latency, then read latency adaptation to memory latency is improved, but system complexity increases
Solution Approach 1:
The patent combines the latency adaptation signaling with the existing data communication protocol. The memory device asserts ready signals on the same bidirectional lines used for data I/O, enabling read latency adaptation to memory latency while avoiding the increased system complexity that would result from adding dedicated signaling infrastructure.
Solution Approach 2:
The data I/O lines are designed to serve multiple functions including data transfer and latency signaling. This multi-functionality enables the system to achieve read latency adaptation to memory latency using the existing universal infrastructure, thereby improving adaptability without increasing system complexity.
Data Source
AI summary
One or more embodiments provide a method and system of reading data from a variable-latency memory, via a serial input/output memory data interface. The system includes a memory having a variable-latency access time, a memory controller, and a serial data bus coupling the memory controller to the memory. The memory controller communicates a Read command to the memory and forces the serial data bus low for a limited time. The memory then forces the bus low and the memory controller then releases the bus. When the memory is ready to provide data, the memory provides a high signal on the serial data bus.