Serial Memory Bus Pipelining Without CS Transaction Restarts
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Solution Overview
Problem
Existing serial bus systems for memory devices face reduced throughput due to the need to restart transactions with each CS signal de-assertion, especially in systems with multiple CPUs or volatile memory types, leading to increased complexity and cost.
Innovation Solution
Implementing a memory device with additional control inputs (CA) to receive operation information during active CS signals, allowing for continuous memory transactions without restarting, including pipelined read operations and extended burst lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the CS signal is used to control memory access transactions, then transaction control and memory access restriction are achieved, but throughput is reduced due to requiring complete restart of transactions after CS de-assertion
Solution Approach 1:
The patent applies preliminary action by receiving operation information during the read latency period (between address reception and data output) while the CS signal remains active. This allows the controller to prepare and queue subsequent transaction parameters in advance, so that when data becomes available, the next transaction can be initiated without waiting for CS re-assertion or completing full transaction cycles. The controller pre-processes operation information during idle latency time, enabling continuous throughput.
2Adaptability or versatility
If multiple CPUs are deployed to increase functionality, then processing capability is improved, but random memory access requests increase leading to reduced overall random access bandwidth
Solution Approach 1:
The patent implements continuity of useful action by enabling the memory controller to maintain continuous operation during the read latency period. Instead of idle waiting between transactions, the controller continuously receives and processes operation information for subsequent transactions during the time when read data is being prepared. This eliminates gaps in useful work, allowing the system to handle increased request volumes from multiple CPUs without reducing per-request bandwidth, as the controller is constantly productive rather than idle between access cycles.
3Speed
If volatile memory (SRAM or DRAM) is used to increase random access speed, then access speed is improved, but system cost and complexity increase due to shadow RAM requirements
Solution Approach 1:
The patent applies self-service by enabling the nonvolatile memory device itself to provide high-speed random access capabilities through its internal architecture and the controller's ability to initiate pipelined transactions. The memory device includes internal buffers and data output circuits that can deliver data at high speeds directly from nonvolatile storage, eliminating the need for external shadow RAM. The controller services itself by efficiently managing transaction queues and utilizing read latency periods to prepare subsequent operations, achieving high-speed access without additional volatile memory components.
Data Source
AI summary
A method can include detecting an active chip select (CS) signal at a CS input of a memory device. Following an active CS signal, a first read instruction and a first address can be received in synchronism with a serial clock at a plurality of serial input/output (SIOs) of the memory device to initiate a first read access. Operation information can be received on at least one control (CA) input after the first read instruction and first address. In response to such operation information, a second read access can be initiated to the memory device. First read data corresponding to the first read access can be driven on the SIOs followed by second read data corresponding to the second read access. Additional follow-on read accesses can be continued with additional operation information on CA input. Corresponding devices and systems are also disclosed.