Serial Memory Chain Architecture for Capacitive Load Reduction
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Solution Overview
Problem
In memory systems, increasing the number of memory devices leads to undesirable characteristics such as increased capacitive load, reduced bandwidth, and decreased operating speed due to cumulative bus capacitance in parallel configurations.
Innovation Solution
Implementing a chain topology with serial bidirectional point-to-point connections between memory devices, allowing a memory controller to selectively access individual devices while bypassing unselected ones, thereby reducing capacitive load and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory devices are arranged in parallel configuration to increase memory capacity, then memory system density is improved, but capacitive load increases and operating speed decreases
Solution Approach 1:
The patent divides the memory system into a chain of individual memory devices, each accessible through sequential addressing. Instead of parallel access to multiple devices simultaneously, the system segments access into discrete time slots where each device is accessed individually in sequence, eliminating the capacitive load penalty of parallel bus access while maintaining high memory capacity.
Solution Approach 2:
The patent implements dynamic switching between memory devices in the chain, where the connection path is reconfigured based on which device needs to be accessed. The system dynamically routes signals through the chain to reach the target device, allowing flexible access to any device in the sequence without requiring all devices to be simultaneously connected to the bus.
2Quantity of substance
If multiple memory devices are connected in parallel to increase bandwidth, then memory capacity is improved, but bus capacitance increases and bandwidth is reduced
Solution Approach 1:
The patent segments the memory access pathway into a serial chain where each device occupies a specific position. Access to the memory system is segmented into discrete operations targeting individual devices, allowing the system to achieve high effective bandwidth through rapid sequential access rather than simultaneous parallel access, thereby avoiding capacitive loading issues.
Solution Approach 2:
The patent ensures continuous useful action by implementing a high-speed serial access mechanism that rapidly cycles through devices in the chain. The system maintains continuous data flow by quickly transitioning between devices, ensuring that the serial access pattern achieves effective bandwidth comparable to or exceeding parallel configurations without suffering from bus capacitance penalties.
3Quantity of substance
If multiple memory devices share a common bus to increase memory density, then memory capacity is improved, but access latency increases due to cumulative capacitance
Solution Approach 1:
The patent segments the memory system into individually addressable devices arranged in a chain, where each device can be accessed with minimal latency. By segmenting the access path and using sequential addressing, the system eliminates the cumulative capacitance effect that plagues shared bus architectures, achieving low-latency access to any device in the chain through direct sequential routing.
Data Source
AI summary
Subject matter disclosed herein relates to memory devices comprising a memory array, a first port to interface with a memory controller directly or indirectly via another memory device, a second port to interface with yet another memory device, and a switch to selectively electrically connect the memory controller to a circuit path leading to the second port or to the memory array, wherein the switch may be responsive to a signal generated by the memory controller.