Serial Memory Interface With Separate EDC Links for Reliable Transfer

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Solution Overview

Problem

Existing serial memory devices face challenges in efficiently transmitting data values and error detection codes over multiple serial data links, where data units and error detection codes are not synchronously transmitted, leading to potential errors and inefficiencies in data transfer.

Innovation Solution

A system and method where data units and error detection codes are transmitted on different serial links, allowing for simultaneous transmission of data values and error detection codes, enabling error detection and correction during read and write operations, with configurations that include multiple serial links for address, data, and error detection codes, ensuring accurate data transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If data units and error detection codes are transmitted on the same serial link, then device complexity is reduced, but data transfer reliability deteriorates due to potential errors without timely detection

Engineering Contradiction:
Improveserial link configurationVSAvoiddata transfer reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent segments the transmission medium into multiple independent serial links, with dedicated links for data units and separate links for error detection codes. This segmentation allows simultaneous transmission of data and error detection information without interference, resolving the contradiction between simplified configuration and reliable error detection.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces separate error detection code links as intermediary channels that carry error detection information independently from data units. This intermediary approach enables the system to maintain simple device configuration while ensuring reliable error detection through dedicated transmission paths.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If data units and error detection codes are transmitted simultaneously on separate serial links, then data transfer reliability is improved, but device complexity increases due to multiple link configurations

Engineering Contradiction:
Improvedata transfer reliabilityVSAvoidserial link configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements universal serial link interfaces that can handle both data units and error detection codes through a standardized multi-link configuration. This multi-functionality approach allows the same interface architecture to support reliable simultaneous transmission without proportionally increasing device complexity, as the links follow uniform design principles.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Device complexity

If error detection codes are transmitted after data units on the same link, then device complexity is minimized, but data transfer efficiency deteriorates due to sequential transmission

Engineering Contradiction:
Improvetransmission configurationVSAvoiddata transfer efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent transitions from sequential transmission on a single link to parallel transmission across multiple links, effectively adding a spatial dimension to the transmission process. This dimensional change enables simultaneous transmission of data units and error detection codes, dramatically improving data transfer efficiency without complicating the fundamental transmission configuration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8464145B2Serial interface devices, systems and methods
Publication Date: 2013.06.11 CYPRESS SEMICONDUCTOR CORP
  • US8464145B2 patent drawing
  • US8464145B2 patent drawing
  • US8464145B2 patent drawing

AI summary

A serial interface device includes multiple serial link connections that receive at least address values and at least one error detection code (EDC) on different serial link connections, the EDC generated from at least the address values, the serial link connections for the address values and EDC operated separately from one another; and multiple output serial links, at least a first one of the output serial links outputting data values read from memory locations corresponding to the address values, and at least a second one of the output serial links different from and operated separately from the first one outputting EDC values generated for the data values read from the memory locations.