Hybrid Serial Memory Interface for Multi-Protocol Low-Latency Packets
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Programmable integrated circuits face challenges in supporting multiple serial memory interface protocols and minimizing acknowledgement processing latency, particularly in environments with limited retransmission buffer sizes, which can reduce link performance.
Innovation Solution
A programmable integrated circuit is designed with a memory interface that combines programmable logic and hardwired logic, featuring a soft memory controller for packet formation, a cyclic redundancy check checking circuit, and a retransmission buffer to manage sequence numbers and acknowledgements, ensuring compatibility with various protocols and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a programmable integrated circuit supports multiple serial memory interface protocols, then compatibility with different memory types is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal memory interface circuit that can operate with multiple serial memory interface protocols (such as HMC and other protocols) through a single unified architecture. The interface includes protocol identification logic that automatically detects the memory type and configures appropriate protocol handling, eliminating the need for separate dedicated interfaces for each protocol and thereby reducing overall device complexity while maintaining broad compatibility.
Solution Approach 2:
The memory interface employs dynamic protocol selection and configuration capabilities. The interface circuitry can adaptively change its operating parameters and protocol behavior based on the detected memory type, allowing a single static hardware structure to dynamically serve multiple protocol requirements without requiring multiple fixed protocol implementations.
2Area of stationary object
If retransmission buffer size is limited, then device area is reduced, but link performance deteriorates due to acknowledgement processing latency
Solution Approach 1:
The patent implements preliminary action by pre-calculating and pre-positioning acknowledgment data in the minimal retransmission buffer before it is needed. The interface circuit prepares acknowledgment sequences in advance based on expected transmission patterns, so that when acknowledgments are needed, they are already available in the buffer, eliminating waiting time and reducing latency without requiring a larger buffer.
Solution Approach 2:
The memory interface maintains continuous useful action by overlapping acknowledgment generation with data transmission operations. While data is being transmitted and buffered, the interface continuously generates and prepares acknowledgments in parallel, ensuring that the acknowledgment pipeline never stalls. This continuous operation eliminates idle time and maintains high link utilization despite limited buffer space.
3Loss of time
If acknowledgement processing latency is minimized, then link performance is improved, but device complexity increases due to additional circuitry
Solution Approach 1:
The patent merges multiple functions into a single integrated acknowledgment processing unit. The circuit combines acknowledgment generation, buffer management, and protocol handling in one unified block, eliminating the need for separate dedicated circuits for each function. This consolidation reduces overall device complexity while maintaining low latency through streamlined signal paths and reduced processing stages.
Solution Approach 2:
The memory interface implements self-service capabilities where the interface circuit automatically generates and manages acknowledgments without requiring external control or intervention. The circuit monitors its own transmission state, autonomously determines when acknowledgments are needed, and handles the entire acknowledgment process internally, reducing latency by eliminating external processing steps while keeping the design relatively simple.
Data Source
AI summary
A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet formation logic that creates packets that include empty fields for sequence number information, acknowledgement information, and cyclic redundancy check information. The hardwired circuitry of the memory interface may be used to insert a sequence number, an acknowledgement, and cyclic redundancy check information into the empty fields.