Serial Memory Interface Segmentation for Scalable Bandwidth
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Solution Overview
Problem
Current computer systems face limitations in scalability and complexity when using parallel communication between processors and memory, especially in architectures where multiple processors share a single memory, due to the need for multiple signal lines and inflexible routing, which hinders bandwidth expansion and performance improvement.
Innovation Solution
A serial communication method and system that converts a parallel communication structure between a processor and memory into a serial communication structure, utilizing a processor-side processor to convert memory transactions into packets and a memory-side processor to access memory, with phases including channel establishment, flow control initialization, and memory transactions, enabling flexible routing and bandwidth expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel communication is used between processor and memory, then bandwidth is increased, but the number of signal lines increases making routing difficult and scalability low
Solution Approach 1:
The parallel communication interface is segmented into multiple serial lanes, where each lane transmits data bits sequentially. The processor-side processor divides the parallel data bus into multiple serial streams, transmitting them through separate physical channels that can be routed independently, thereby reducing routing complexity while maintaining total bandwidth through aggregation of multiple lanes.
Solution Approach 2:
The patent transitions from a two-dimensional parallel bus structure to a multi-dimensional serial architecture by adding the time dimension. Data is transmitted serially over time across multiple lanes rather than simultaneously across a single parallel bus, enabling flexible routing through spatial distribution of data streams while achieving equivalent or higher bandwidth through temporal multiplexing.
2Ease of operation
If parallel communication structure is used, then communication between processor and memory is established, but implementation difficulty and complexity are high in multi-processor architectures
Solution Approach 1:
The serial communication interface is designed with universal protocols and standardized packet formats that can be used across multiple processor types and memory configurations. The same serial interface logic handles both single-processor and multi-processor scenarios, eliminating the need for complex parallel interface variations and reducing implementation difficulty in multi-processor systems through unified communication methodology.
Solution Approach 2:
The patent introduces processor-side processors as intermediary devices that convert parallel processor interfaces into serial communication protocols. These intermediaries handle protocol conversion, packetization, and flow control, shielding the complexity of parallel-to-serial transformation from the actual processor and memory components, thereby simplifying overall system implementation.
3Adaptability or versatility
If serial communication is used, then scalability and routing flexibility are improved, but conversion from parallel structure requires additional interface components
Solution Approach 1:
The patent merges the functions of parallel-to-serial conversion, packetization, flow control, and error handling into integrated processor-side processors and memory-side processors. By combining multiple interface functions into unified serial communication controllers, the design reduces the number of separate components needed compared to implementing distinct conversion modules for each function, thereby achieving routing flexibility with minimized interface complexity.
Data Source
AI summary
Provided are serial communication method and system for memory access. The serial communication system for memory access includes a processor-side processor that receives a memory transaction from a processor and converts the memory transaction into a packet according to a predetermined phase to serially transmit the packet; a memory-side processor that receives the serially transmitted packet according to the predetermined phase and converts the packet into the memory transaction to access a memory, wherein the predetermined phase includes a channel establishment phase, a flow control initialization phase, and a memory transaction phase.