Serial-to-Parallel Memory Manager for High-Bandwidth Processor Interfaces
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Solution Overview
Problem
The increasing computing capability of processors leads to a high requirement for memory bandwidth, which is limited by crosstalk in parallel bus transmission, resulting in a 'memory wall' issue where the working frequency of parallel interfaces is severely limited, unable to meet the bandwidth needs.
Innovation Solution
A memory manager with a serial-to-parallel conversion interface circuit is introduced, allowing data to be transmitted between the processor and memory through a serial interface, increasing the working frequency and reducing crosstalk, while a cache prefetching circuit predicts and stores data to offset the memory delay caused by serial-to-parallel conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If parallel bus transmission is used to increase memory bandwidth, then data transmission capacity is improved, but crosstalk between interfaces increases and working frequency is limited
Solution Approach 1:
The patent replaces the traditional parallel bus mechanical transmission system with a serial transmission system using optical or electrical serial interfaces. This substitution eliminates the crosstalk problem inherent in parallel bus structures by using sequential data transmission through fewer channels, allowing higher working frequencies without the interference that plagues parallel interfaces.
Solution Approach 2:
The patent changes the transmission mode parameter from parallel to serial, fundamentally altering how data is transmitted between processor and memory. This parameter change enables higher working frequencies because serial transmission does not suffer from the crosstalk limitations that constrain parallel bus operating frequencies, thereby increasing memory bandwidth despite using fewer physical channels.
2Object-affected harmful factors
If working frequency of parallel interface is reduced to decrease crosstalk, then crosstalk is reduced, but memory bandwidth cannot meet processor requirements
Solution Approach 1:
The patent substitutes the parallel interface mechanical system with a serial transmission system that is not constrained by crosstalk. This allows the working frequency to be increased significantly beyond what is possible with parallel interfaces, as the serial transmission medium does not exhibit the same interference characteristics, thereby achieving high memory bandwidth without frequency reduction.
3Quantity of substance
If more parallel interfaces are added to increase memory bandwidth, then data transmission capacity is improved, but processor area is exceeded
Solution Approach 1:
The patent segments the data transmission into sequential serial channels rather than requiring multiple simultaneous parallel interfaces. By dividing the data stream into time-sequential segments transmitted through fewer physical channels, the solution achieves equivalent or superior bandwidth capacity without requiring the large processor area that would be needed for multiple parallel interface structures.
Solution Approach 2:
The patent transitions from a spatial dimension approach (multiple parallel interfaces requiring more area) to a temporal dimension approach (serial transmission using time-sequential data flow). This dimensional change allows high bandwidth to be achieved through time-multiplexed serial channels rather than space-multiplexed parallel interfaces, significantly reducing the required processor area.
4Speed
If serial interface is used to increase working frequency, then working frequency is improved, but data transmission capacity decreases
Solution Approach 1:
The patent employs periodic action by using high-frequency serial transmission with time-sequential data encoding. The rapid periodic transmission of data bits in serial form, combined with efficient encoding schemes, allows the high working frequency to translate into substantial data transmission capacity over time, compensating for the single-channel nature of serial transmission.
Data Source
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AI summary
A memory manager, a processor memory subsystem, a processor, and an electronic device are disclosed. The memory manager may be disposed between the memory and the processor. One end of the memory manager is connected to the processor by using a serial line, and the other end of the memory manager is connected to the memory by using a parallel line. In this way, the processor may be provided with a serial interface instead of a parallel interface. Because crosstalk in a serial transmission manner is low, a working frequency corresponding to the serial interface may be set to a higher value. Therefore, although a bus bit width of a group of serial interfaces is less than a bus bit width of a group of parallel interfaces, because the working frequency of the serial interface is higher than a working frequency of the parallel interface, and an increased memory bandwidth brought by an increase in the working frequency is greater than a decreased memory bandwidth caused by a decrease in the bus bit width, a memory bandwidth can be effectively improved, so that a data transmission rate between the processor and the memory is improved.