Write Data Path for Time-Shared Serial Memory Write Masking
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Solution Overview
Problem
Modern processors with multiple cores sharing a single memory access port face computing speed issues due to collisions, and existing multi-port and pseudo-dual-port memories increase memory complexity and die space.
Innovation Solution
A serial read write memory with a write mask mechanism that includes a write driver logic circuit to control write driver transistors, allowing simultaneous read and write operations without corrupting data by floating bit lines during write mask operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If separate read and write ports are used, then memory access speed is improved, but memory complexity and die space increase
Solution Approach 1:
The memory access cycle is segmented into distinct phases: a read phase during the first portion of the clock cycle where the bit line is charged, and a write phase during the second portion where the bit line is floated. This temporal segmentation allows the same physical infrastructure to support both read and write operations without requiring separate ports, thereby maintaining high access speed while reducing memory complexity and die space.
2Adaptability or versatility
If pseudo-dual-port operation is used, then separate read and write access is achieved, but word line repeated pulsing increases operation complexity
Solution Approach 1:
The bit line impedance is dynamically changed during the operation cycle. During the read phase, the bit line is charged to a defined voltage level. During the write phase, the bit line is floated (high impedance state) to prevent data corruption. This dynamic impedance control enables the memory to handle both read and write operations through a single access port without requiring complex repeated word line pulsing, thereby reducing operation complexity while maintaining adaptability.
3Adaptability or versatility
If write mask is implemented without floating bit lines, then write masking functionality is achieved, but data corruption occurs in accessed bitcells
Solution Approach 1:
Before the write operation is executed, the bit line is pre-charged during the read phase. Then, when write masking is detected, the bit line is floated (placed in high impedance state) before the write data is driven onto it. This preliminary floating action prevents any write data from being inadvertently transferred to the bitcell, ensuring data integrity while maintaining the flexibility of write masking functionality.
Data Source
AI summary
A serial read write memory is provided in which a write driver logic circuit controls a write driver to drive the bit lines in a selected column responsive to a binary value of a data in signal during a write operation in which a write mask signal is not asserted. Should the write mask signal be asserted, the write driver logic circuit controls the write driver to charge the bit line in the selected column and then to float the bit lines regardless of the binary value of the data in signal during a write operation.