Serial Multiply Accumulator Reducing XOR Gates and Registers
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Solution Overview
Problem
Conventional serial architectures for finite field multiply accumulators require high hardware complexity and resource usage, particularly in terms of XOR gates and registers, which limits their area efficiency in digital communication systems.
Innovation Solution
A reconfigured serial multiply accumulator design that reduces the number of XOR gates and registers by rearranging the circuit structure, allowing for efficient operation of two multiplications and one addition over Galois fields with fewer elements, while maintaining similar performance to conventional designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional serial architecture is used for finite field multiply accumulator, then hardware complexity and resource usage are high, but area efficiency is limited
Solution Approach 1:
The patent merges two finite field multipliers and one finite field adder into a unified serial multiply accumulator structure. The shared computational resources (AND gates, XOR gates, registers) are combined to perform multiple operations (A×B and C×D multiplications plus addition) with reduced hardware overhead compared to separate implementation of each operation.
Solution Approach 2:
The serial multiply accumulator is designed as a universal structure that can perform multiple finite field operations (multiplication and addition) using the same hardware resources. The circuit can process different input pairs (A,B) and (C,D) through the same sequence of computational stages, making the hardware multi-functional rather than requiring dedicated circuits for each operation type.
2Productivity
If parallel architecture is used to achieve fast calculating speed, then hardware complexity becomes too high for area-efficient design
Solution Approach 1:
The patent employs dynamic resource allocation where the same hardware resources (computational units, registers) are reused across different operational phases. The circuit dynamically switches between performing multiplication operations and addition operations using the same physical components, rather than having static dedicated hardware for each function, thereby reducing overall hardware complexity while maintaining operational efficiency.
Solution Approach 2:
The serial multiply accumulator operates through periodic cycles where computational resources are alternately allocated to different operations. The circuit performs multiplication in one phase, then addition in the next phase, using the same hardware resources in a time-multiplexed manner. This periodic reuse of resources achieves the required computational throughput without requiring all resources to be simultaneously available, thus reducing hardware complexity.
Data Source
AI summary
A serial multiply accumulator (MAC) for operation of two multiplications and one addition over Galois field is disclosed. The MAC includes a first element feeding circuit, a second element feeding circuit, a number of first calculating circuits and a second calculating circuit. By re-arranging the circuit design, many elements used in the conventional MAC, such as XOR gates and registers, can be saved. The present invention has an advantage of lower area cost.