Serial NOR Flash Memory Row Decoder Timing Relaxation
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Solution Overview
Problem
Existing serial flash memory technologies face challenges in relaxing timing requirements for row addresses, reducing the area of row decoders, and row drive circuits, which are high in performance and occupy a large area.
Innovation Solution
The introduction of a row enable signal in the control module of the serial flash memory, enabling the internal row address to be valid before the read process starts, allowing the row decoder to decode the internal row address earlier, and the row drive circuit to operate accordingly, thereby reducing the performance and area requirements of the row decoder and row drive circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the row decoder and row drive circuit are designed with high performance to meet strict timing requirements, then the timing requirements are satisfied, but the area occupied by these circuits increases
Solution Approach 1:
The patent applies preliminary action by enabling the row decoder earlier in the address transmission process. Specifically, the row decoder is enabled after receiving the most significant bits of the row address (before the least significant bits are transmitted), allowing it to begin decoding准备工作 in advance. This reduces the timing pressure on the row decoder and row drive circuit, enabling them to use simpler, smaller designs while still meeting the overall timing requirements for the complete address decode operation
2Measurement precision
If the row decoder and row drive circuit are designed with high performance to ensure accurate decoding, then the decoding accuracy is improved, but the device complexity increases
Solution Approach 1:
The patent reduces device complexity by performing preliminary decoding operations. The row decoder starts decoding the row address bits as they are received serially, beginning with the most significant bits, rather than waiting for the complete address to be transmitted. This preliminary action allows the use of simpler decoding logic that processes bits incrementally, reducing the overall complexity of the row decoder and row drive circuit while maintaining decoding accuracy
3Reliability
If the timing requirement on row address is made strict to ensure proper operation, then the operation reliability is improved, but the productivity decreases due to longer transmission time
Solution Approach 1:
The patent improves productivity by implementing preliminary action in the address decoding process. The row decoder is enabled and begins processing the row address bits as soon as the most significant bits are received, rather than waiting for the complete address transmission to finish. This overlapping of address transmission and decoding operations reduces the critical path timing requirements, allowing faster overall operation while maintaining reliability
Solution Approach 2:
The patent applies dynamics by making the row decoder enable timing flexible rather than fixed. The row decoder can be enabled at different points during the address transmission sequence, allowing the system to optimize the balance between timing requirements and transmission speed. This dynamic timing approach enables faster productivity while ensuring proper decoding operation
Data Source
AI summary
The present application discloses a serial flash memory, including a memory array, a row decoder, a column decoder, a control module, and an SPI interface, wherein the control module includes a row enable signal; and when the last bit of an SPI row address in an SPI address signal is to be read, the control module enables the row enable signal, and the row enable signal enables an internal row address of an internal address of the serial flash memory to be valid and enables the row decoder to perform decoding and select the internal row address. The present application further provides an address control method of a serial flash memory. In the present application, the timing requirement on the row address can be relaxed, the area of the row decoder can be reduced, and the area of the row drive circuit can be reduced.