Serial Output Circuits for Sub-UI Phase Correction

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Solution Overview

Problem

Existing FPGA-based serial output circuits struggle with fine phase adjustments of less than one unit interval (UI) and are limited in dynamic phase change applications, especially in direct digital RF systems, due to the difficulty in adjusting phase on a scale of several tens to several hundreds of serial output circuits.

Innovation Solution

An output signal generation device comprising two or more signal output blocks with serial output circuits and a signal multiplexer, along with a phase correction unit that controls the phase of the output signals by adjusting the amplitude of the signals, enabling fine phase adjustments through electrical multiplexing and amplitude control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If delay adjustment function is used in serial output circuits, then skew between adjacent channels is reduced, but fine adjustment of less than one UI is difficult

Engineering Contradiction:
Improvephase adjustment precisionVSAvoidadjustment capability
Core Design Contradiction:
Manufacturing precisionVSEase of operation

Solution Approach 1:

The phase adjustment function is segmented into two independent parts: delay adjustment for coarse correction of skew between adjacent channels, and amplitude adjustment for fine correction of phase differences. This segmentation allows each part to optimize its specific function without interference from the other.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from one-dimensional delay adjustment to two-dimensional adjustment by adding amplitude control as a new dimension. This allows phase correction to occur in both time domain (delay) and amplitude domain, enabling fine adjustment of less than one UI that was previously unachievable.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If delay adjustment is performed on a scale of several tens to several hundreds of serial output circuits, then phase matching across array antenna elements is achieved, but the existing delay adjustment function is not suitable

Engineering Contradiction:
Improvescalability to array antennaVSAvoidphase matching accuracy
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The serial output circuit is enhanced with multi-functionality by adding amplitude adjustment capability to the existing delay adjustment function. This universalized circuit can now handle both coarse delay correction and fine phase adjustment, making it suitable for large-scale array antenna applications requiring phase matching across dozens to hundreds of elements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Device complexity

If low bit quantized signal is used in direct digital RF, then transmission signal is simplified, but continuous phase rotation by signal processing is difficult

Engineering Contradiction:
Improvesignal processing complexityVSAvoidphase adjustment capability
Core Design Contradiction:
Device complexityVSEase of operation

Solution Approach 1:

The invention replaces the mechanical/signal-processing-based phase rotation approach with an amplitude control mechanism. Instead of attempting continuous phase rotation through complex signal processing of low-bit quantized signals, the system uses amplitude adjustment of the quantized signals to achieve fine phase control, substituting a simpler control mechanism for a complex one.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS12395258B2Output signal generation device, control circuit, storage medium, and phase correction method
Publication Date: 2025.08.19 MITSUBISHI ELECTRIC CORP
  • US12395258B2 patent drawing
  • US12395258B2 patent drawing
  • US12395258B2 patent drawing

AI summary

An output signal generation device includes: two or more signal output blocks that each include two or more serial output circuits and a signal multiplex unit, the serial output circuits controlling amplitudes of data signals having different delay times and each outputting a first serial signal, the signal multiplex unit electrically multiplexing the first serial signals outputted from the two or more serial output circuits, and output a second serial signal obtained by electrical multiplex of the signal multiplex unit; and a phase correction unit that controls a phase of the second serial signal outputted from the two or more signal output blocks by changing the amplitude of the first serial signal outputted from the serial output circuit.