Serial-to-Parallel Conversion With Delayed Clocks for High-Frequency Data
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Solution Overview
Problem
Conventional serial to parallel conversion devices face difficulties in operating at high frequencies, leading to non-logic operations between shift and parallel registers due to the absence of additional clock signals, resulting in high operation frequencies that hinder data delivery from the parallel register to the next register.
Innovation Solution
A serial/parallel data conversion apparatus utilizing a frequency divider and a delay controller with three-stage registers to convert serial data into parallel data without an additional serial working clock signal, reducing the operation frequency at the parallel terminal through frequency division and delayed clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If serial data conversion is operated under high frequency, then conversion speed is improved, but the parallel register becomes difficult to realize logic operation and data delivery fails
Solution Approach 1:
The patent divides the conversion process into three distinct stages using three separate registers: a first register for receiving serial data, a second register for intermediate parallel storage, and a third register for final parallel output. This segmentation allows each stage to operate at appropriate frequencies, with the parallel registers operating at lower frequencies to ensure reliable logic operations while the overall conversion maintains high speed through the pipelined architecture.
Solution Approach 2:
The patent introduces a delay circuit as an intermediary component between the frequency divider and the parallel registers. This delay circuit generates delayed clock signals that coordinate the timing between different register stages, ensuring that data is properly transferred between registers at reduced frequencies while maintaining the high-speed conversion capability through the intermediary timing control.
2Speed
If additional serial working clock signal is not inputted, then operation frequency of parallel register can be reduced, but data cannot be delivered from parallel register to next register
Solution Approach 1:
The patent employs dynamic clock signal generation where the delay circuit produces different clock phases and frequencies as needed. The system dynamically adjusts clock timing to enable data transfer between registers at reduced frequencies while maintaining productivity through the dynamic coordination of multiple clock signals generated by the delay circuit and frequency divider.
Solution Approach 2:
The patent uses periodic clock signals generated by the frequency divider and delay circuit to control data transfer between registers. The frequency divider creates periodic clock signals at reduced frequencies, and the delay circuit introduces controlled phase delays to these periodic signals, enabling synchronized periodic data transfer between the three register stages without requiring additional high-frequency clock inputs.
3Speed
If frequency divider and delay controller are added, then operation frequency at parallel terminal is lowered, but device complexity increases
Solution Approach 1:
The frequency divider serves multiple functions: it divides the input clock frequency to generate slower clock signals for parallel register operation, and it provides the base clock signal that the delay circuit then processes further. This multi-functionality reduces the need for separate dedicated circuits, thereby limiting the increase in device complexity while achieving frequency reduction.
Solution Approach 2:
The patent implements a nested structure where the delay circuit is connected to and processes the output of the frequency divider, creating a hierarchical arrangement. The delay circuit nests within the clock generation system by taking the divided clock signal as input and generating the final delayed clock signals needed for the parallel registers. This nesting approach consolidates the complexity into a structured, integrated unit rather than scattered components.
Data Source
AI summary
A serial/parallel data conversion apparatus and a method thereof are used to convert serial data into parallel data by a delay pulse and three stage registers, wherein the device includes a first data register, a second data register, a third data register, a frequency divider and a delay controller. Moreover, the first data register converts the serial data into the parallel data according to a first working clock signal. The frequency divider performs a frequency division for the first working clock signal for producing a second working clock signal. The second data register acquires the parallel data from the first register according to the second working clock signal. The delay controller delays the second working clock signal to produce a third working clock signal. Finally, the third data register obtains the parallel data from the second register according to the third working clock signal.