Serial-to-Parallel I/O Circuit With Immediate Bit Output
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Solution Overview
Problem
Existing I/O circuits face inefficiencies due to insufficient output pins, leading to slow data transmission rates as they require all sequential logic circuits to be fully written before outputting data, which affects system performance.
Innovation Solution
An I/O circuit with M sequential logic circuits in series, each comprising two D-type flip-flops, a multiplexer, and a D-type latch, allowing for simultaneous input and output of data bits without waiting for full data sets, using an enable control signal to determine whether to output new or previously stored data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If sequential logic circuits are used to extend output pins, then the number of I/O pins is increased, but the data transmission speed becomes slow because all circuits must be fully written before output
Solution Approach 1:
The I/O circuit is divided into multiple independent sequential logic circuits, each capable of independent operation. Each circuit processes one bit of data through its own D-type flip-flop, latch, and multiplexer, allowing parallel processing of multiple bits rather than sequential processing of a single bit through all circuits.
Solution Approach 2:
The multiplexer dynamically switches between two data paths based on the enable control signal: one path allows new data to pass through to the latch, while the other path allows previously latched data to be output. This dynamic switching enables the circuit to adapt its behavior based on whether data is being written or read, resolving the contradiction between extending pin count and maintaining high transmission speed.
2Quantity of substance
If a single pin with multi-function is used, then the number of pins is reduced, but the operating speed decreases and additional chip select pins are required
Solution Approach 1:
Each sequential logic circuit is designed with universal functionality to handle both data input and data output operations. The multiplexer enables the same circuit infrastructure to serve dual purposes: accepting new data during write operations and outputting stored data during read operations, eliminating the need for separate dedicated input and output pins for each bit.
3Reliability
If all sequential logic circuits must be fully written before output, then data integrity is maintained, but the overall data transmission time increases
Solution Approach 1:
The circuit maintains continuous useful action by allowing overlapping write and read operations. While one circuit is writing new data, other circuits can simultaneously output previously latched data. The enable control signal coordinates these operations to ensure data integrity is maintained while maximizing the utilization of all circuit resources, preventing idle time and maintaining continuous productive operation.
Data Source
AI summary
A serial to parallel I/O circuit apparatus includes M sequential logic circuits and each of them includes a first D-type flip-flop for receiving one bit of input data, and the output of each the first D-type flip-flop connects to the input of a first D-type flip-flop of a next stage. A second D-type flip-flop receives one bit of enable control signal, and the output of each of the second D-type flip-flops connects to the input of a second D-type flip-flop of a next stage. A multiplexer contains two input terminals and an enable control signal receiving terminal, wherein one input terminal is used to receive the input data received by the first D-type flip-flop, and the enable control signal receiving terminal receives the enable control signal received by the second D-type flip-flop. A D-type latch outputs the data, and the output data is fed back to another input terminal of the multiplexer so as to be selected as a data output when a next set of data are input.