Serial-to-Parallel Converter Circuit for 6-Bit and 8-Bit LCD Input
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Solution Overview
Problem
Existing serial-to-parallel converter circuits in LCD modules are limited to supporting only 6-bit serial data, requiring separate improvements in both the LCD module and microcomputer to handle 8-bit data, which complicates system development and increases costs by necessitating changes to existing devices.
Innovation Solution
A serial-to-parallel converter circuit that identifies the number of input bits using a count value from the serial clock and generates appropriate parallel data by shifting and holding serial data, allowing it to support both m-bit and n-bit input modes without requiring additional control input terminals on the microcomputer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a serial-to-parallel converter circuit is improved to support 8-bit serial data, then the functionality and adaptability are improved, but the device complexity and system development cost increase due to requiring additional control input terminals and software improvements on the microcomputer side
Solution Approach 1:
The serial-to-parallel converter circuit automatically identifies whether 6-bit or 8-bit serial data is being input by counting the number of serial clock cycles during data transfer. This self-identification mechanism eliminates the need for external control signals or mode selection terminals, allowing the circuit to adapt to different data widths autonomously
Solution Approach 2:
The circuit changes its operational parameters dynamically based on the detected data width. By monitoring the serial clock cycle count, the circuit adjusts its internal shift register configuration and parallel output generation accordingly, supporting both 6-bit and 8-bit modes without hardware modification
2Adaptability or versatility
If a serial-to-parallel converter circuit is improved to support 8-bit serial data by adding control input terminals, then the adaptability is improved, but the ease of operation deteriorates because software improvements are needed on the microcomputer side
Solution Approach 1:
The converter circuit performs automatic mode detection by counting serial clock cycles, eliminating the need for software-based mode selection on the microcomputer side. The circuit serves itself by autonomously determining the data width and configuring its internal operations accordingly
Solution Approach 2:
The mode identification function is extracted from the microcomputer's software domain and embedded within the hardware circuit itself. This transfers the intelligence from software to hardware, simplifying the microcomputer's role to merely providing the serial data and clock signals
3Adaptability or versatility
If separate improvements are made to both the LCD module and microcomputer to handle 8-bit data, then the functionality is improved, but the productivity decreases due to extended system development time
Solution Approach 1:
The serial-to-parallel converter circuit is designed with multi-functionality to handle both 6-bit and 8-bit serial data inputs using the same hardware architecture. This universal design allows a single circuit implementation to serve multiple data width requirements without needing separate development paths
Data Source
AI summary
A serial-to-parallel converter circuit comprising: an m-bit serial data holding unit to be input with serial data whose input bit number is set to m or n (<m) bits within a transfer period and a serial clock synchronized therewith, and to shift and hold the serial data by one bit based on the serial clock; an input mode identifying unit to identify whether the input bit number is m or n bits, based on a count value obtained by counting the number of generation of the serial clock during the transfer period; and a parallel data generating unit to output the held m-bit data as first parallel data when the input bit number is identified as m bits, and to output m-bit data obtained by adding predetermined (m−n)-bit data to the held n-bit data as second parallel data when the input bit number is identified as n bits.