Serial-Parallel Testbench Verification for FPGA Systems
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Solution Overview
Problem
The complexity of large systems implemented on target devices like FPGAs and ASICs requires efficient testing for parallelism, but existing methods using serial testbenches fail to accurately assess the parallel nature of these systems, leading to incomplete performance evaluation.
Innovation Solution
A method is introduced that creates two instances of the system, one running serially and the other in parallel, with the serial instance processing input vectors faster to resolve data dependencies and generate results used by the parallel instance, allowing for accurate performance evaluation and verification of serial consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a serial testbench is used to test the system, then the testbench can be created in high-level language format, but the testbench cannot accurately assess the parallel nature of the system
Solution Approach 1:
The patent divides the testing process into two separate testbenches: a serial testbench for creating input vectors and a parallel testbench for evaluating parallel performance. This segmentation allows each testbench to be optimized for its specific purpose while maintaining overall testing accuracy.
Solution Approach 2:
The patent introduces an intermediary component that translates and coordinates between the serial testbench output and the parallel testbench input. This intermediary ensures data consistency while enabling the parallel evaluation of system performance.
2Ease of operation
If a serial testbench is used, then the testbench operation is simple, but the performance evaluation is incomplete
Solution Approach 1:
The testing functionality is segmented into two distinct testbenches with specialized roles. The serial testbench handles simple input generation while the parallel testbench performs comprehensive performance evaluation, ensuring both ease of operation and evaluation completeness.
Solution Approach 2:
The patent merges the advantages of both serial and parallel testing approaches by combining a simple serial testbench for input generation with a comprehensive parallel testbench for performance evaluation, achieving both operational simplicity and evaluation completeness.
3Measurement precision
If the system is tested in parallel, then the parallel nature is assessed accurately, but the testbench complexity increases
Solution Approach 1:
The complex parallel testing functionality is segmented into a dedicated parallel testbench that handles only parallel evaluation tasks. This separates the complexity from the main serial testbench, allowing each component to remain relatively simple while achieving accurate parallelism assessment.
4Productivity
If the serial instance processes input vectors faster, then data dependencies are resolved, but the processing rate mismatch complicates verification
Solution Approach 1:
The patent implements feedback mechanisms where the serial testbench generates input vectors that are fed to both the serial and parallel instances. The results from both instances are compared and verified, with feedback loops ensuring consistency despite different processing rates. This feedback approach manages verification complexity while maintaining high productivity.
Data Source
AI summary
A method for designing a system on a target device includes performing high-level compilation on a high-level language source file to generate a hardware description language (HDL) of the system and a serial testbench for the system. Verification is performed on the system that examines a parallel nature of the system by using the serial testbench.